|
CY24272 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – Rambus® XDR™ Clock Generator with Zero SDA Hold Time | |||
|
CY24272
Rambus® XDR⢠Clock Generator with
Zero SDA Hold Time
Features
â Meets Rambus® Extended Data Rate (XDRâ¢) clocking
requirements
â 25 ps typical cycle-to-cycle jitter
â â135 dBc/Hz typical phase noise at 20 MHz offset
â 100 or 133 MHz differential clock input
â 300â667 MHz high speed clock support
â Quad (open drain) differential output drivers
â Supports frequency multipliers: 3, 4, 5, 6, 9/2 and 15/4
â Spread Awareâ¢
â 2.5V operation
â 28-pin TSSOP package
Table 1. Device Comparison
CY24271
SDA hold time = 300 ns
(SMBus compliant)
RRC = 200Ω typical
(Rambus standard drive)
CY24272
SDA hold time = 0 ns
(I2C compliant)
RRC = 295Ω minimum
(Reduced output drive)
Logic Block Diagram
/BYPASS
EN
Bypass
MUX
REFCLK,REFCLKB
PLL
EN
RegA
EN
RegB
EN
RegC
CLK0
CLK0B
CLK1
CLK1B
CLK2
CLK2B
EN
RegD
CLK3
CLK3B
SCL
SDA
ID0
ID1
Cypress Semiconductor Corporation ⢠198 Champion Court
Document Number: 001-42414 Rev. **
⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised November 9, 2007
[+] Feedback
|
▷ |