CY23FP12-002 Datasheet, PDF (8/10 Pages) Cypress Semiconductor – 200-MHz Field Programmable Zero Delay Buffer

Switching Characteristics for CY23FP12-002SC/I ^[5]
Parameter
Description
t_tsk
Tracking Skew
t_LOCK
T_LD
PLL Lock Time^[5]
Inserted Loop Delay
Test Conditions
Input reference clock @ < 50-KHz modulation
with ±3.75% spread
Stable power supply, valid clock at REF
Max loop delay for PLL Lock (stable
frequency)
Max loop delay to meet Tracking Skew Spec
Min.
Switching Waveforms
Duty Cycle Timing
t₁
t₂
1.4V
1.4V
1.4V
CY23FP12-002
Typ.
Max. Unit
200
ps
1.0
ms
7
ns
4
ns
All Outputs Rise/Fall Time
2.0V
OUTPUT _0.8V
t₃
Output-Output Skew
2.0V
0.8V
t₄
3.3V
0V
OUTPUT
1.4V
OUTPUT
1.4V
t₅
Input-Output Propagation Delay
INPUT
V_DD/2
FBK
t₆
V_DD/2
Device-Device Skew
FBK, Device 1
V_DD/2
FBK, Device 2
t₇
V_DD/2
Document #: 38-07644 Rev. **
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