CY23FP12-002 Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 200-MHz Field Programmable Zero Delay Buffer

CY23FP12-002
200-MHz Field Programmable Zero Delay Buffer
Features
• Pre-programmed Configurations
• Fully field-programmable
— Input and output dividers
— Inverting/noninverting outputs
— Phase-locked loop (PLL) or fanout buffer configu-
ration
• 10-MHz to 200-MHz operating range
• Split 2.5V or 3.3V outputs
• Two LVCMOS reference inputs
• Twelve low-skew outputs
— Output-output skew < 200 ps
— Device-device skew < 500 ps
• Input-output skew < 250 ps
• Cycle-cycle jitter < 100 ps (typical)
• Three-stateable outputs
• < 50-µA shutdown current
• Spread Aware
• 28-pin SSOP
• 3.3V operation
• Industrial temperature available
Block Diagram
VDDC
Lock Detect
REFSEL
REF1
REF2
FBK
÷M
100 to
÷1
400MHz
÷N
PLL
÷2
÷3
÷4
÷X
÷2X
Function
S[2:1] ^Selection
VSSC
Test Logic
Functional Description
The CY23FP12-002 is a pre-programmed version of the
CY23FP12. It features a high-performance fully field-program-
mable 200 MHz zero delay buffer designed for high speed
clock distribution. The integrated PLL is designed for low jitter
and optimized for noise rejection. These parameters are
critical for reference clock distribution in systems using high-
performance ASICs and microprocessors.
The CY23FP12-002 is fully programmable via volume or
prototype programmers enabling the user to define an appli-
cation-specific Zero Delay Buffer with customized input and
output dividers, feedback topology (internal/external), output
inversions, and output drive strengths. For additional flexibility,
the user can mix and match multiple functions, listed in
Table 2, and assign a particular function set to any one of the
four possible S1-S2 control bit combinations. This feature
allows for the implementation of four distinct personalities,
selectable with S1-S2 bits, on a single programmed silicon.
The CY23FP12-002 also features a proprietary auto-power-
down circuit that shuts down the device in case of a REF
failure, resulting in less than 50 µA of current draw.
The CY23FP12-002 provides twelve outputs grouped in two
banks with separate power supply pins which can be
connected independently to either a 2.5V or a 3.3V rail.
Selectable reference input is a fault tolerance feature which
allows for glitch-free switch over to secondary clock source
when REFSEL is asserted/de-asserted.
VDDA
CLKA0
CLKA1
CLKA2
CLKA3
CLKA4
CLKA5
VSSA
VDDB
CLKB0
CLKB1
CLKB2
CLKB3
CLKB4
CLKB5
VSSB
Pin Configuration
SSOP
Top View
REF2 1
REF1 2
CLKB0 ³
CLKB1 4
V_SSB
5
CLKB2 ⁶
CLKB3 ⁷
V_DDB
8
V_SSB
9
CLKB4 ¹⁰
CLKB5 ¹¹
V_DDB
12
V_DDC
13
S2 ¹⁴
28 REFSEL
27 _FBK
26 CLKA0
25 CLKA1
24
V_SSA
23 CLKA2
22 CLKA3
21
V_DDA
20
V_SSA
19 CLKA4
18 CLKA5
17
V_DDA
16
V_SSC
15 S1
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07644 Rev. **
Revised February 25, 2004