S25FL128S Datasheet, PDF (79/149 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

S25FL128S/S25FL256S
Figure 9.15 ECC Status Register Read Command Sequence
CS#
0 1 2 3 4 5 6 7 8 9 10 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55
SCK
Instruction
32-Bit
Address
Dummy Byte
SI
7 6 5 4 3 2 1 0 31 30 29
321 0 76543210
SO
High Impedance
DATA OUT 1
DATA OUT 2
7 6 54 3 2 1 07
MSB
MSB
9.3.12
AutoBoot
SPI devices normally require 32 or more cycles of command and address shifting to initiate a read command. And, in order to read
boot code from an SPI device, the host memory controller or processor must supply the read command from a hardwired state
machine or from some host processor internal ROM code.
Parallel NOR devices need only an initial address, supplied in parallel in a single cycle, and initial access time to start reading boot
code.
The AutoBoot feature allows the host memory controller to take boot code from an S25FL128S and S25FL256S device immediately
after the end of reset, without having to send a read command. This saves 32 or more cycles and simplifies the logic needed to
initiate the reading of boot code.
 As part of the power up reset, hardware reset, or command reset process the AutoBoot feature automatically starts a read
access from a pre-specified address. At the time the reset process is completed, the device is ready to deliver code from
the starting address. The host memory controller only needs to drive CS# signal from high to low and begin toggling the
SCK signal. The S25FL128S and S25FL256S device will delay code output for a pre-specified number of clock cycles
before code streams out.
– The Auto Boot Start Delay (ABSD) field of the AutoBoot register specifies the initial delay if any is needed by the host.
– The host cannot send commands during this time.
If ABSD = 0, the maximum SCK frequency is 50 MHz.
– If ABSD > 0, the maximum SCK frequency is 133 MHz if the QUAD bit CR1[1] is 0 or 104 MHz if the QUAD bit is set to 1.
 The starting address of the boot code is selected by the value programmed into the AutoBoot Start Address (ABSA) field of
the AutoBoot Register which specifies a 512-byte boundary aligned location; the default address is 00000000h.
– Data will continuously shift out until CS# returns high.
 At any point after the first data byte is transferred, when CS# returns high, the SPI device will reset to standard SPI mode;
able to accept normal command operations.
– A minimum of one byte must be transferred.
– AutoBoot mode will not initiate again until another power cycle or a reset occurs.
 An AutoBoot Enable bit (ABE) is set to enable the AutoBoot feature.
The AutoBoot register bits are non-volatile and provide:
 The starting address (512-byte boundary), set by the AutoBoot Start Address (ABSA). The size of the ABSA field is 23 bits
for devices up to 32-Gbit.
 The number of initial delay cycles, set by the AutoBoot Start Delay (ABSD) 8-bit count value.
 The AutoBoot Enable.
If the configuration register QUAD bit CR1[1] is set to 1, the boot code will be provided 4 bits per cycle in the same manner as a
Read Quad Out command. If the QUAD bit is 0 the code is delivered serially in the same manner as a Read command.
Document Number: 001-98283 Rev. *J
Page 79 of 149