S25FL128S Datasheet, PDF(58/149 Page) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

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S25FL128S Datasheet, PDF (58/149 Pages) SPANSION – MirrorBit® Flash Non-Volatile Memory CMOS 3.0 Volt Core with Versatile I/O Serial Peripheral Interface with Multi-I/O

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S25FL128S/S25FL256S

â OTP Byte Programming (OTPP)

8.3 Block Protection

The Block Protect bits (Status Register bits BP2, BP1, BP0) in combination with the Configuration Register TBPROT bit can be used

to protect an address range of the main flash array from program and erase operations. The size of the range is determined by the

value of the BP bits and the upper or lower starting point of the range is selected by the TBPROT bit of the configuration register.

Table 8.1 Upper Array Start of Protection (TBPROT = 0)

Status Register Content

BP2

BP1

BP0

Protected Fraction of

Memory Array

None

Upper 64th

Upper 32nd

Upper 16th

Upper 8th

Upper 4th

Upper Half

All Sectors

Protected Memory (kbytes)

FL128S

128 Mb

FL256S

256 Mb

256

512

1024

2048

4096

8192

16384

32768

Table 8.2 Lower Array Start of Protection (TBPROT = 1)

Status Register Content

BP2

BP1

BP0

Protected Fraction of

Memory Array

None

Lower 64th

Lower 32nd

Lower 16th

Lower 8th

Lower 4th

Lower Half

All Sectors

Protected Memory (kbytes)

FL128S

128 Mb

FL256S

256 Mb

256

512

1024

2048

4096

8192

16384

32768

When Block Protection is enabled (i.e., any BP2-0 are set to 1), Advanced Sector Protection (ASP) can still be used to protect

sectors not protected by the Block Protection scheme. In the case that both ASP and Block Protection are used on the same sector

the logical OR of ASP and Block Protection related to the sector is used. Recommendation: ASP and Block Protection should not be

used concurrently. Use one or the other, but not both.

8.3.1

Freeze Bit

Bit 0 of the Configuration Register is the FREEZE bit. The FREEZE bit locks the BP2-0 bits in Status Register 1 and the TBPROT bit

in the Configuration Register to their value at the time the FREEZE bit is set to 1. Once the FREEZE bit has been written to a logic 1

it cannot be cleared to a logic 0 until a power-on-reset is executed. As long as the FREEZE bit is cleared to logic 0 the status register

BP bits and the TBPROT bit of the Configuration Register are writable. The FREEZE bit also protects the entire OTP memory space

from programming when set to 1. Any attempt to change the BP bits with the WRR command while FREEZE = 1 is ignored and no

error status is set.

Document Number: 001-98283 Rev. *J

Page 58 of 149

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