S6J3120 Datasheet, PDF (74/141 Pages) Cypress Semiconductor – This section explains the Cortex-R5 CPU core

S6J3120 Series
10.4.4 Power-on Conditions
(TA: Recommended operating conditions, VSS=0.0 V)
Parameter
Symbol
Pin
Name
Condition
s
Min
Value
Typ
Max
Unit
Remarks
Level detection
voltage
-
VCC
-
Level detection
hysteresis width
-
VCC
-
Level detection
time
-
-
-
Level release
voltage
-
VCC
-
Power off time
-
VCC
-
2.15
2.35
2.55
-
100
-
-
-
540
2.25
2.45
2.65
1
-
-
V
mV
μs *1
V
ms *2
VCC:
Power ramp rate
dV/dt VCC
0.2V to
–
–
6
mV/µs *3
2.55V
Maximum ramp
VCC:
rate guaranteed to
not generate
|dV/dt|
VCC
Between
2.6V and
–
–
50
mV/µs ^*4
power-on reset
4.5V
*1: _{If a power fluctuation precedes the low-voltage detection time, the detection may occur or be canceled after the supply voltage}
passes the detection voltage range.
*2: _{If VCC is held below 0.2V for a minimum period of tOFF, power-on reset will occur. If tOFF is not satisfied, power-on reset will still}
occur if the power ramp rate is kept below 6mV/µs.
*3: _{This is the power ramp rate with which power-on reset will always occur regardless of power-off time, as mentioned in *2.}
*4: _{When VCC is within 2.6V - 4.5V, and VCC fluctuation is below 50mV/us, the power-on reset is suppressed. Between 4.5V - 5.5V,}
the power-on reset does not occur with any VCC fluctuation.
Note:
When neither *2 nor *3 can be satisfied, assert external reset (RSTX) at power-up and at any brownout event.
 Power off time, Power ramp rate at Power-on
tOFF
VCC
0.2V
0.2V
dV/dt
 Maximum ramp rate guaranteed to not generate power-on reset
VCC
|dV/dt|
5.5V
4.5V
|dV/dt|
2.6V
Document Number: 002-04863 Rev.*D
Page 74 of 141