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S6J3120 Datasheet, PDF (1/141 Pages) Cypress Semiconductor – This section explains the Cortex-R5 CPU core | |||
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S6J3120 Series
32-Bit Traveo⢠Family
Microcontroller Datasheet
This section provides an overview of the S6J3120 series. The S6J3120 series is a set of 32-bit microcontrollers designed for
in-vehicle use. It uses the ARM® Cortex-R5 CPU as a CPU.
Features
This section explains the features of the S6J3120 series.
Cortex-R5 Core
ï®This section explains the Cortex-R5 CPU core.
ï¯ ARM® Cortex®-R5
ï¯ 32-bit ARM architecture
⢠2-instruction issuance super scalar
⢠8-stage pipeline
ï¯ ARMv7/Thumb®-2 instruction set
ï¯ MPU (memory protection) equipped
⢠16-area support
ï¯ ECC support for the TCM ports for RAM
1-bit error correction and 2-bit error detection
(SEC-DED)
ï¯ TCM ports
2 TCM ports
⢠ATCM port
⢠BTCM port (B0TCM, B1TCM)
ï¯ Caches
⢠Instruction cache 16 KB
⢠Data cache 16 KB
ï¯ VIC port
Low latency interrupt
ï¯ AXI master interface
64-bit AXI interface (instruction/data access)
32-bit AXI interface (I/O access)
ï¯ AXI slave interface
64-bit AXI interface (TCM port access)
ï¯ ETM-R5 trace
Peripheral Functions
This section explains peripheral functions.
ï®Clock generation
ï¯ Main clock oscillation (4 MHz)
ï¯ No sub clock oscillation
ï¯ CR oscillation (100 kHz)
ï¯ CR oscillation (4 MHz)
ï®Built-in Flash memory size
ï¯ Program: 1024 K + 64 KB (S6J312AHzC*)/768 K + 64 KB
(S6J3129HzC*)/512 K + 64 KB (S6J3128HzC*)
ï¯ *z: A/B
ï¯ Work: 112 KB (S6J312AHzC*)/ 112 KB
(S6J3129HzC*)/112 KB (S6J3128HzC*)
ï¯ *z: A/B
ï®Built-in RAM size
ï¯ TCRAM 64 KB(S6J312AHzC*)/ 48 KB(S6J3129HzC*)/32
KB(S6J3128HzC*)
ï¯ System SRAM 16 KB (S6J312AHzC*)/ 16 KB
(S6J3129HzC*)/ 16 KB (S6J3128HzC*)
ï¯ Backup RAM 8 KB (S6J312AHzC*)/ 8 KB
(S6J3129HzC*)/8 KB (S6J3128HzC*)
ï¯ *z: A/B
ï®General-purpose ports: 112 channels (S6J312AHzC*)/ 112
channels (S6J3129HzC*)/ 112 channels (S6J3128HzC*)
ï¯ *z: A/B
ï®External bus interface
ï¯ 24-bit address, 16bit data
ï®DMA controller
ï¯ Up to 16 channels can be activated simultaneously.
ï®A/D converter (successive approximation type)
ï¯ 12-bit resolution, 2 units mounted: Max 50 channels (22
channels + 28 channels)(S6J312AHzC*)/ Max 50 channels
(22 channels + 28 channels)(S6J3129HzC*)/ Max 50
channels (22 channels + 28 channels)(S6J3128HzC*)
ï¯ *z: A/B
ï®External interrupt input: 16 channels
ï¯ Level ("H"/"L") and edge (rising/falling) can be detected.
ï®Multi-function serial (transmission and reception FIFOs
mounted) :Max 10 channels(S6J312AHzC*)/ Max 10
channels(S6J3129HzC*)/ Max 10 channels(S6J3128HzC*)
ï¯ *z: A/B
<I2C>
ï¯ Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
ï¯ Standard mode (Max. 100kbps) is supported only.
ï¯ DMA transfer is supported.
<UART (asynchronous serial interface) >
ï¯ Full duplex, double buffering system; 64-byte transmission
FIFO, 64-byte reception FIFO
ï¯ Parity check can be enabled/disabled.
ï¯ Built-in dedicated baud rate generator
ï¯ An external clock can be used as a transfer clock.
ï¯ Parity, frame, overrun error detection functions are
available.
ï¯ DMA transfer is supported.
Cypress Semiconductor Corporation
Document Number: 002-04863 Rev.*D
⢠198 Champion Court ⢠San Jose, CA 95134-1709 ⢠408-943-2600
Revised December 15, 2016
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