CY8C34 Datasheet, PDF (71/99 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C34 Family Data Sheet
11.5.2 Delta-Sigma ADC
Table 11-19. 12-Bit Delta-Sigma ADC DC Specifications
Parameter
Description
Resolution^[9]
Number of channels - single ended
Conditions
THD
Number of channels - differential Differential pair is formed using a
pair of GPIOs
Monotonicity^[9]
Gain error
Input buffer bypassed
Input offset voltage
Current consumption
192 ksps, 12-bit mode,
ADC clock = 6.144 MHz^[9]
Input voltage range - single
ended^[9]
Input voltage range - differential^[9]
Input voltage range - differential
(buffered)^[9]
Input resistance^[9]
Input buffer used
Total harmonic distortion^[9]
Input buffer bypassed, 12 bits, ADC
clock = 6.144 MHz, gain = 1
Input buffer used
Table 11-20. 12-Bit Delta-Sigma ADC AC Specifications
Parameter
PSRR
CMRR
Description
Startup time^[9]
Power supply rejection ratio^[9]
Common mode rejection ratio^[9]
Sample rate
SNR
INL
DNL
Signal-to-noise ratio (SNR)
Input bandwidth^[9]
Integral non linearity^[9]
Differential non linearity^[9]
Conditions
Input buffer used
Input buffer used
ADC clock = 6.144 MHz,
continuous sample mode, input
buffer bypassed
ADC clock = 3.072 MHz,
continuous sample mode, input
buffer used
Vdda ≥ 2.7V, input buffer bypassed
Min
8
-
-
Yes
-
-
-
Vssa
Vssa
Vssa
10
-
-
Min
-
90
90
-
-
70
-
-
-
Typ
Max
Units
-
12
bits
-
No. of
GPIO
-
No. of
GPIO/2
-
-
-
±0.2
%
-
±0.1
mV
-
3.75
mA
-
Vdda
V
-
Vdda
V
- Vdda - 1 V
-
-
MΩ
148^[12]
-
kΩ
-
0.0032
%
Typ
Max
Units
-
4
samples
-
-
dB
-
-
dB
-
192
ksps
-
160
ksps
-
-
dB
44
-
kHz
-
1
LSB
-
1
LSB
11.5.3 Voltage Reference
Table 11-21. Voltage Reference Specifications
Parameter
Description
Vref
Precision reference for the
Delta-Sigma ADC
Conditions
Min
1.015
(-0.9%)
Typ
1.024
Max
1.033
(+0.9%)
Units
V
Note
12. Holding the gain and number of bits constant, the input resistance is proportional to the inverse of the clock frequency.
Document Number: 001-53304 Rev. *B
Page 71 of 99
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