CY8C34 Datasheet, PDF (55/99 Pages) Cypress Semiconductor – Programmable System-on-Chip (PSoC)

PRELIMINARY
PSoC^®3: CY8C34 Family Data Sheet
The TIA configuration is used for applications where an external
sensor's output is current as a function of some type of stimulus
such as temperature, light, magnetic flux etc. In a common appli-
cation, the voltage DAC output can be connected to the VREF
TIA input to allow calibration of the external sensor bias current
by adjusting the voltage DAC output voltage.
8.6 LCD Direct Drive
The PSoC Liquid Crystal Display (LCD) driver system is a highly
configurable peripheral designed to allow PSoC to directly drive
a broad range of LCD glass. All voltages are generated on chip,
eliminating the need for external components. With a high
multiplex ratio of up to 1/16, the CY8C34 family LCD driver
system can drive a maximum of 736 segments. The PSoC LCD
driver module was also designed with the conservative power
budget of portable devices in mind, enabling different LCD drive
modes and power down modes to conserve power.
PSoC Creator provides an LCD segment drive component. The
component wizard provides easy and flexible configuration of
LCD resources. You can specify pins for segments and
commons along with other options. The software configures the
device to meet the required specifications. This is possible
because of the programmability inherent to PSoC devices.
Key features of the PSoC LCD segment system are:
„ LCD panel direct driving
„ Type A (standard) and Type B (low power) waveform support
„ Wide operating voltage range support (2V to 5V) for LCD
panels
„ Static, 1/2, 1/3, 1/4, 1/5 bias voltage levels
„ Internal bias voltage generation through internal resistor ladder
„ Up to 62 total common and segment outputs
„ Up to 1/16 multiplex for a maximum of 16 backplane/common
outputs
„ Up to 62 front plane/segment outputs for direct drive
„ Drives up to 736 total segments (16 backplane x 46 front plane)
„ Up to 128 levels of software controlled contrast
„ Ability to move display data from memory buffer to LCD driver
through DMA (without CPU intervention)
„ Adjustable LCD refresh rate from 10 Hz to 150 Hz
„ Ability to invert LCD display for negative image
„ Three LCD driver drive modes, allowing power optimization
Figure 8-9. LCD System
Global
Clock
LCD
DAC
UDB
PIN
LCD Driver
Block
DMA
Display
RAM
PHUB
8.6.1 LCD Segment Pin Driver
Each GPIO pin contains an LCD driver circuit. The LCD driver
buffers the appropriate output of the LCD DAC to directly drive
the glass of the LCD. A register setting determines whether the
pin is a common or segment. The pin’s LCD driver then selects
one of the six bias voltages to drive the I/O pin, as appropriate
for the display data.
8.6.2 Display Data Flow
The LCD segment driver system reads display data and
generates the proper output voltages to the LCD glass to
produce the desired image. Display data resides in a memory
buffer in the system SRAM. Each time you need to change the
common and segment driver voltages, the next set of pixel data
moves from the memory buffer into the Port Data Registers via
DMA.
8.6.3 UDB and LCD Segment Control
A UDB is configured to generate the global LCD control signals
and clocking. This set of signals is routed to each LCD pin driver
through a set of dedicated LCD global routing channels. In
addition to generating the global LCD control signals, the UDB
also produces a DMA request to initiate the transfer of the next
frame of LCD data.
8.6.4 LCD DAC
The LCD DAC generates the contrast control and bias voltage
for the LCD system. The LCD DAC produces up to five LCD drive
voltages plus ground, based on the selected bias ratio. The bias
voltages are driven out to GPIO pins on a dedicated LCD bias
bus, as required.
Document Number: 001-53304 Rev. *B
Page 55 of 99
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