Z9972 Datasheet, PDF (7/9 Pages) Cypress Semiconductor – 3.3V, 125-MHz, Multi-Output Zero Delay Buffer

Z9972
AC Parameters V_DD = 2.9V to 3.6V, V_DDC = 3.3V ±10%, T_A = –40°C to +85°C^[7]
Parameters
Description
Conditions
Min.
Tr/Tf
TCLK Input Rise/Fall
Fref
Reference Input Frequency
Note 8
Fxtal
Crystal Oscillator Frequency
see Table 3
10
FrefDC
Reference Input Duty Cycle
25
Fvco
PLL VCO Lock Range
200
Tlock
Maximum PLL lock Time
Tr/Tf
Output Clocks Rise/Fall Time^[9]
0.8V to 2.0V
0.15
Fout
Maximum Output Frequency
Q (÷2)
Q (÷4)
Q (÷6)
FoutDC
tpZL, tpZH
tpLZ, tpHZ
TCCJ
TSKEW
Tpd
Output Duty Cycle^[9]
Output Enable Time^[9](all outputs)
Output Disable Time^[9](all outputs)
Cycle to Cycle Jitter^[9](peak to peak)
Any Output to Any Output Skew^{[9, 10]}
Propagation Delay^{[10, 11]}
TCLK0
Q (÷8)
QFB = (÷8)
TCYCLE/2 – 750
2
2
–270
TCLK1
–330
Typ.
±100
250
130
70
Max.
3.0
Note 8
25
75
480
10
1.2
125
120
80
60
TCYCLE/2 + 750
10
8
350
530
470
Unit
ns
MHz
MHz
%
MHz
ms
ns
MHz
ps
ns
ns
ps
ps
ps
Table 3. Crystal Oscillator Frequency
Parameter
Description
Conditions
Min. Typ.
Max.
Units
T_C
T_S
T_A
C_L
R_ESR
Frequency Tolerance
Frequency Temperature
Stability
Aging
Load Capacitance
Effective Series Resistance
(ESR)
Note 12
(T_A –10 to +60°C)^[12]
(first 3 years @ 25°C)^[12]
The crystal’s rated load^[12]
Note 13
±100
±100
PPM
PPM
5
PPM/Yr.
20
pF
40
80
Ohms
Notes:
7. Parameters are guaranteed by design and characterization. Not 100% tested in production.
8. Maximum and minimum input reference is limited by VC0 lock range.
9. Outputs loaded with 30 pF each.
10. 50Ω transmission line terminated into V_DD/2.
11. Tpd is specified for a 50 MHz input reference. Tpd does not include jitter.
12. For best performance and accurate frequencies from this device, It is recommended but not mandatory that the chosen crystal meet or exceed these
specifications.
13. Larger values may cause this device to exhibit oscillator startup problems.
Document #: 38-07088 Rev. *D
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