W181 Datasheet, PDF (7/9 Pages) Cypress Semiconductor – Peak Reducing EMI Solution

W181
Application Information
Recommended Circuit Configuration
For optimum performance in system applications the power
supply decoupling scheme shown in Figure 4 should be used.
V_DD decoupling is important to both reduce phase jitter and
EMI radiation. The 0.1-µF decoupling capacitor should be
placed as close to the V_DD pin as possible, otherwise the in-
creased trace inductance will negate its decoupling capability.
The 10-µF decoupling capacitor shown should be a tantalum
type. For further EMI protection, the V_DD connection can be
made via a ferrite bead, as shown.
Recommended Board Layout
Figure 5 shows a recommended 2-layer board layout.
Reference Input
1
NC ₂
GND ₃
4
8
7
6
5
R1
Clock
Output
C1
0.1 µF
3.3 or 5V System Supply
FB
C2
10 µF Tantalum
Figure 4. Recommended Circuit Configuration
Reference Input
NC
G
C1 =
C2 =
R1 =
High frequency supply decoupling
capacitor (0.1-µF recommended).
Common supply low frequency
decoupling capacitor (10-µF tantalum
recommended).
Match value to line impedance
FB = _{Ferrite Bead}
G ₌ Via To GND Plane
C1
G
Power Supply Input
(3.3 or 5V)
R1
G
C2
FB
Figure 5. Recommended Board Layout (2-Layer Board)
Ordering Information
Ordering Code
Freq. Mask
Code
W181
01, 02, 03
51, 52, 53
W181
01
Document #: 38-00790-B
Package
Name
G
Package Type
8-pin Plastic SOIC (150-mil)
X
14-pin Plastic TSSOP
Clock Output
7