W134S Datasheet, PDF (7/12 Pages) Cypress Semiconductor – Direct Rambus Clock Generator

W134M/W134S
Table 8. State Transition Latency Specifications (continued)
Transition
E
E
F
L
N
B,D
Transition Latency
From
To
Parameter Max.
Description
Clk Stop
Normal
t_CLKON
10 ns Time from StopB until Clk/ClkB provides glitch-free
clock edges.
Clk Stop
Normal
t_CLKSETL 20 cycles Time from StopB to Clk/ClkB output settled to within 50
ps of the phase before CLK/CLKB was disabled.
Normal
Test
Clk Stop
Normal
t_CLKOFF
t_CTL
Normal
Test
t_CTL
Normal or Clk Stop Power-down t_POWERDN
5 ns
3 ms
3 ms
1 ms
Time from StopB to Clk/ClkB output disabled.
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t_DISTLOCK).
Time from when S0 or S1 is changed until CLK/CLKB
output has resettled (excluding t_DISTLOCK).
Time from PwrDnB to the device in Power-down.
Figure 5 shows that the Clk Stop to Normal transition goes
through three phases. During t_CLKON, the clock output is not
specified and can have glitches. For t_CLKON < t < t_CLKSETL, the
clock output is enabled and must be glitch-free. For
t > t_CLKSETL, the clock output phase must be settled to within
50 ps of the phase before the clock output was disabled. At
this time, the clock output must also meet the voltage and
timing specifications of Table . The outputs are in a
high-impedance state during the Clk Stop mode.
Table 9. Distributed Loop Lock Time Specification
Parameter
Description
Min. Max. Unit
t_DISTLOCK Time from when Clk/ClkB output is settled to when the phase error between SynclkN and
PclkM falls within the t_ERR,PD spec in Table .
5
ms
Table 10.Supply and Reference Current Specification
Parameter
I_POWERDOWN
I_CLKSTOP
I_NORMAL
I_REF,PWDN
I_REF,NORM
Description
Min. Max. Unit
“Supply” current in Power-down state (PwrDnB 1 = 0)
– 250 µA
“Supply” current in Clk Stop state (StopB = 0)
–
65 mA
“Supply” current in Normal state (StopB = 1,PwrDnB = 1)
– 100 mA
Current at VDDIR or VDDIPD reference pin in Power-down state (PwrDnB = 0)
–
50 µA
Current at VDDIR or VDDIPD reference pin in Normal or Clk Stop state (PwrDnB = 1) –
2
mA
Document #: 38-07426 Rev. *B
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