CY7C4292 Datasheet, PDF (7/16 Pages) Cypress Semiconductor – 64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion

Depth Expansion Configuration
The CY7C4282/92 can easily be adapted to applications
requiring more than 64K/128K words of buffering. Figure 3
shows Depth Expansion using three CY7C4282/92s. Maximum
depth is limited only by signal loading. Follow these steps:
1. The first device must be designated by grounding the First
Load (FL) control input.
2. All other devices must have FL in the HIGH state.
3. The Expansion Out (XO) pin of each device must be tied to
the Expansion In (XI) pin of the next device.
4. EF and FF composite flags are created by O-Ring together
each individual respective flag.
CY7C4282
CY7C4292
XO
WCLK ^RCLK
WEN
REN
RS
OE
7C4282
D 7C4292 Q
V_CC
FL
FF
EF
XI
DATAIN (D)
XO
WCLK
RCLK
WEN
REN
RS
OE
7C4282
D 7C4292 Q
V_CC
FL
FF
EF
XI
DATA OUT (Q)
WRITECLOCK (WCLK)
WRITEENABLE (WEN)
RESET (RS)
XO
WCLK RCLK
WEN
REN
RS 7C4282 OE
D 7C4292 Q
READ CLOCK (RCLK)
READ ENABLE (REN)
OUTPUTENABLE (OE)
FF
FF
EF
EF
FL XI
FIRST LOAD (FL)
Figure 3. Block Diagram of 64Kx9/128Kx9 One Meg Deep Sync FIFO Memory
with Programmable Flags used in Depth Expansion Configuration
Document #: 38-06009 Rev. *B
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