CY7C4292 Datasheet, PDF (2/16 Pages) Cypress Semiconductor – 64K/128K x 9 Deep Sync FIFOs with Retransmit and Depth Expansion

Pin Configuration
STQFP
Top View
WEN
1
RS
2
D₈
3
D₇
4
D₆
5
N/C
6
N/C
7
N/C
8
N/C
9
N/C
10
N/C
11
N/C
12
D₅
13
D₄
14
D₃
15
D₂
16
CY7C4282
CY7C4292
48
Q₅
47
Q₄
46
GND
45
Q₃
44
Q₂
43
V_CC
42
Q₁
41
Q₀
40
GND
39
N/C
38
FF
37
EF
36
OE
35
GND
34
FL/RT
33
N/C
CY7C4282
CY7C4292
Selection Guide
Maximum Frequency
Maximum Access Time
Minimum Cycle Time
Minimum Data or Enable Set-up
Minimum Data or Enable Hold
Maximum Flag Delay
Active Power Supply Current (I_CC)
Commercial
Industrial
7C4282/92-10
100
8
10
3
0.5
8
40
45
7C4282/92-15
66.7
10
15
4
1
10
40
7C4282/92-25
40
15
25
6
1
15
40
Unit
MHz
ns
ns
ns
ns
ns
mA
Density
Package
CY7C4282
64k x 9
64-pin 10x10 STQFP
CY7C4292
128k x 9
64-pin 10x10 STQFP
Pin Definitions
Signal
Name
D_{0 − 8}
Q_{0 − 8}
WEN
Description
Data Inputs
Data Outputs
Write Enable
REN
Read Enable
WCLK Write Clock
I/O
Description
I Data Inputs for 9-bit bus.
O Data Outputs for 9-bit bus.
I The only write enable when device is configured to have programmable flags. Data is
written on a LOW-to-HIGH transition of WCLK when WEN is asserted and FF is HIGH.
I Enables the device for Read operation. REN must be asserted LOW to allow a read
operation.
I The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full. When
LD is asserted, WCLK writes data into the programmable flag-offset register.
Document #: 38-06009 Rev. *B
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