CY7C1516KV18_11 Datasheet, PDF (7/33 Pages) Cypress Semiconductor – 72-Mbit DDR II SRAM 2-Word Burst Architecture

CY7C1516KV18, CY7C1527KV18
CY7C1518KV18, CY7C1520KV18
Pin Definitions
Pin Name
I/O
Pin Description
DQ_[x:0]
LD
Input Output- Data input output signals. Inputs are sampled on the rising edge of K and K clocks during valid write
Synchronous operations. These pins drive out the requested data when the read operation is active. Valid data is driven
out on the rising edge of both the C and C clocks during read operations or K and K when in single clock
mode. When read access is deselected, Q_[x:0] are automatically tristated.
CY7C1516KV18 − DQ_[7:0]
CY7C1527KV18 − DQ_[8:0]
CY7C1518KV18 − DQ_[17:0]
CY7C1520KV18 − DQ_[35:0]
Input- Synchronous load. This input is brought LOW when a bus cycle sequence is defined. This definition
Synchronous includes address and read/write direction. All transactions operate on a burst of 2 data.
NWS₀,
NWS₁
Input- Nibble Write Select 0, 1 − Active LOW (CY7C1516KV18 Only). Sampled on the rising edge of the K and
Synchronous K clocks during write operations. Used to select which nibble is written into the device during the current
portion of the write operations. Nibbles not written remain unaltered.
NWS₀ controls D_[3:0] and NWS₁ controls D_[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS₀,
BWS₁,
BWS₂,
BWS₃
Input- Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks during
Synchronous write operations. Used to select which byte is written into the device during the current portion of the write
operations. Bytes not written remain unaltered.
CY7C1527KV18 − BWS₀ controls D_[8:0]
CY7C1518KV18 − BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
CY7C1520KV18 − BWS₀ controls D_[8:0], BWS₁ controls D_[17:9], BWS₂ controls D_[26:18] and BWS₃ controls
D_[35:27].
All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A, A0
Input- Address inputs. These address inputs are multiplexed for both read and write operations. Internally, the
Synchronous device is organized as 8M x 8 (2 arrays each of 4M x 8) for CY7C1516KV18 and 8M x 9 (2 arrays each
of 4M x9) for CY7C1527KV18, 4M x 18 (2 arrays each of 2M x 18) for CY7C1518KV18, and 2M x 36 (2
arrays each of 1M x 36) for CY7C1520KV18.
CY7C1516KV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1527KV18 – Since the least significant bit of the address internally is a “0,” only 22 external address
inputs are needed to access the entire memory array.
CY7C1518KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
22 address inputs are needed to access the entire memory array.
CY7C1520KV18 – A0 is the input to the burst counter. These are incremented in a linear fashion internally.
21 address inputs are needed to access the entire memory array. All the address inputs are ignored when
the appropriate port is deselected.
R/W
Input- Synchronous read or write input. When LD is LOW, this input designates the access type (read when
Synchronous R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold times
around edge of K.
C
Input Clock Positive input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See application example for further details.
C
Input Clock Negative input clock for output data. C is used in conjunction with C to clock out the read data from the
device. C and C can be used together to deskew the flight times of various devices on the board back to
the controller. See application example for further details.
K
Input Clock Positive input clock input. The rising edge of K is used to capture synchronous inputs to the device and
to drive out data through Q_[x:0] when in single clock mode. All accesses are initiated on the rising edge of K.
K
Input Clock Negative input clock input. K is used to capture synchronous data being presented to the device and to
drive out data through Q_[x:0] when in single clock mode.
Document Number: 001-00437 Rev. *J
Page 7 of 33
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