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CY7C1323AV25 Datasheet, PDF (7/18 Pages) Cypress Semiconductor – 18-Mbit 4-Word Burst SRAM with DDR-I Architecture
PRELIMINARY
CY7C1323AV25
Maximum Ratings
(Above which the useful life may be impaired.)
Storage Temperature ..................................... −65°C to +150°C
Ambient Temperature with
Power Applied.................................................. −55°C to +125°C
Supply Voltage on VDD Relative to GND.........−0.5V to +3.6V
DC Applied to Outputs in High-Z...........−0.5V to VDDQ + 0.5V
DC Input Voltage[11] ................................−0.5V to VDDQ + 0.5V
Electrical Characteristics Over the Operating Range[13]
DC Electrical Characteristics
Current into Outputs (LOW)......................................... 20 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
Latch-up Current.................................................... > 200 mA
Operating Range
Ambient
Range Temperature (TA)
Com’l
0°C to +70°C
VDD[12]
2.5 ± 0.1V
VDDQ[12]
1.4V to 1.9V
Parameter
Description
VDD
VDDQ
VOH
VOL
VOH(LOW)
VOL(LOW)
VIH
VIL
VIN
IX
IOZ
VREF
IDD
Power Supply Voltage
I/O Supply Voltage
Output HIGH Voltage
Output LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage[11]
Input LOW Voltage[11, 16]
Clock Input Voltage
Input Load Current
Output Leakage Current
Input Reference Voltage[17]
VDD Operating Supply
ISB1
Automatic
Power-Down
AC Input Requirements
Parameter
Description
VIH
Input High (Logic 1) Voltage
VIL
Input Low (Logic 0) Voltage
Test Conditions
Min.
2.4
1.4
Note 14
Note 15
IOH = –0.1 mA, Nominal Impedance
IOL = 0.1 mA, Nominal Impedance
VDDQ/2 – 0.12
VDDQ/2 – 0.12
VDDQ – 0.2
VSS
VREF + 0.1
–0.3
–0.3
GND ≤ VI ≤ VDDQ
GND ≤ VI ≤ VDDQ, Output Disabled
Typical Value = 0.75V
–5
–5
0.68
VDD = Max., IOUT = 0 mA, 100 MHz
f = fMAX = 1/tCYC
133 MHz
167 MHz
Max. VDD, Both Ports 100 MHz
Deselected, VIN ≥ VIH or
VIN ≤ VIL f = fMAX = 1/tCYC,
Inputs Static
133 MHz
167 MHz
Test Conditions
Min.
VREF + 0.2
–
Typ.
2.5
1.5
0.75
Typ.
–
–
Max.
Unit
2.6
V
1.9
V
VDDQ/2 + 0.12 V
VDDQ/2 + 0.12 V
VDDQ
V
0.2
V
VDDQ + 0.3 V
VREF – 0.1 V
VDDQ + 0.3 V
5
µA
5
µA
0.95
V
590
mA
620
mA
650
mA
360
mA
380
mA
400
mA
Max.
–
VREF – 0.2
Unit
V
V
Thermal Resistance[18]
Parameter
Description
Test Conditions
165 FBGA Package
ΘJA
Thermal Resistance (Junction to Ambient) Test conditions follow standard test
16.7
ΘJC
Thermal Resistance (Junction to Case)
methods and procedures for measuring
thermal impedance, per EIA/JESD51.
2.5
Notes:
11. Overshoot: VIH(AC) < VDDQ + 0.85V (Pulse width less than tCYC/2). Undershoot: VIL(AC) > –1.5V (Pulse width less than tCYC/2).
12. Power-up: Assumes a linear ramp from 0V to VDD(min.) within 200 ms. During this time VIH < VDD and VDDQ < VDD.
13. All Voltage referenced to Ground.
14. Output are impedance controlled. IOH = –(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ω.
15. Output are impedance controlled. IOL=(VDDQ/2)/(RQ/5) for values of 175Ω <= RQ <= 350Ωs.
16. This spec is for all inputs except C and C Clock. For C and C Clock, VIL(Max.) = VREF – 0.2V.
17. VREF (Min.) = 0.68V or 0.46VDDQ, whichever is larger, VREF (Max.) = 0.95V or 0.54VDDQ, whichever is smaller.
18. Tested initially and after any design or process change that may affect these parameters.
Unit
°C/W
°C/W
Document #: 38-05501 Rev. *A
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