CY7C1323AV25 Datasheet, PDF (5/18 Pages) Cypress Semiconductor – 18-Mbit 4-Word Burst SRAM with DDR-I Architecture

Application Example^[1]
PRELIMINARY
CY7C1323AV25
DQ
A
SRAM#1
ZQ
CQ/CQ#
LD# R/W# C C# K K#
R = 250ohms
DQ
BUS
Addresses
MASTER Cycle Start#
(CPU
R/W#
or
Return CLK
ASIC)
Source CLK
Return CLK#
Source CLK#
Echo Clock1/Echo Clock#1
Echo Clock2/Echo Clock#2
Vterm = 0.75V
R = 50ohms
Vterm = 0.75V
DQ
SRAM#2
ZQ
CQ/CQ#
A LD# R/W# C C# K K#
R = 250ohms
Truth Table^{[2, 3, 4, 5, 6, 7]}
Operation
Write Cycle:
Load address; wait one cycle;
input write data on 2 consec-
utive K and K rising edges.
Read Cycle:
Load address; wait one cycle;
read data on 2 consecutive C
and C rising edges.
NOP: No Operation
Standby: Clock Stopped
K
L-H
L-H
L-H
Stopped
LD
L
L
H
X
R/W
DQ
L^[8] D(A1)at
K(t+1)↑
H^[9] Q(A1) at
C(t+1)↑
DQ
D(A2) at
K(t+1)↑
Q(A2) at
C(t+1) ↑
DQ
DQ
D(A3) at K(t+2) D(A4) at
↑
K(t+2) ↑
Q(A3) at
C(t+2)↑
Q(A4) at
C(t+2) ↑
X
High-Z
High-Z
High-Z)
High-Z
X
Previous State Previous State Previous State Previous State
Linear Burst Address Table
First Address (External) Second Address (Internal) Third Address (Internal) Fourth Address (Internal)
X..X00
X..X01
X..X10
X..X11
X..X01
X..X10
X..X11
X..X00
X..X10
X..X11
X..X00
X..X01
X..X11
X..X00
X..X01
X..X10
Notes:
1. The above application shows 2 DDR-I being used.
2. X = “Don't Care“, H = Logic HIGH, L = Logic LOW, ↑ represents rising edge.
3. Device will power-up deselected and the outputs in a three-state condition.
4. “A1” represents address location latched by the devices when transaction was initiated. A2, A3 and A4 represents the internal address sequence in the burst.
5. “t“ represents the cycle at which a Read/Write operation is started. t+1 and t+2 are the first and second clock cycles succeeding the “t” clock cycle.
6. Data inputs are registered at K and K rising edges. Data outputs are delivered on C and C rising edges, except when in single clock mode.
7. It is recommended that K = K and C = C when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging
symmetrically.
8. This signal was HIGH on previous K clock rise. Initiating consecutive Write operations on consecutive K clock rises is not permitted. The device will ignore the
second Write request.
9. This signal was LOW on previous K clock rise. Initiating consecutive Read operations on consecutive K clock rises is not permitted. The device will ignore the
second Read request.
Document #: 38-05501 Rev. *A
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