CY7C11611KV18 Datasheet, PDF (7/29 Pages) Cypress Semiconductor – 18-Mbit QDR® II+ SRAM 4-Word Burst Architecture (2.5 Cycle Read Latency)

CY7C11611KV18, CY7C11761KV18
CY7C11631KV18, CY7C11651KV18
Table 2. Pin Definitions
Pin Name
I/O
Pin Description
D_[x:0]
WPS
NWS₀,
NWS₁,
Input- Data Input Signals. Sampled on the rising edge of K and K clocks when valid write operations are active.
Synchronous CY7C11611KV18  D_[7:0]
CY7C11761KV18  D_[8:0]
CY7C11631KV18  D_[17:0]
CY7C11651KV18  D_[35:0]
Input- Write Port Select  Active LOW. Sampled on the rising edge of the K clock. When asserted active, a
Synchronous write operation is initiated. Deasserting deselects the write port. Deselecting the write port ignores D_[x:0].
Input- Nibble Write Select 0, 1  Active LOW (CY7C11611KV18 Only). Sampled on the rising edge of the K
Synchronous and K clocks when write operations are active. Used to select which nibble is written into the device
during the current portion of the write operations. NWS₀ controls D_[3:0] and NWS₁ controls D_[7:4].
All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write Select
ignores the corresponding nibble of data and it is not written into the device.
BWS₀,
BWS₁,
BWS₂,
BWS₃
Input- Byte Write Select 0, 1, 2 and 3  Active LOW. Sampled on the rising edge of the K and K clocks when
Synchronous write operations are active. Used to select which byte is written into the device during the current portion
of the write operations. Bytes not written remain unaltered.
CY7C11761KV18 BWS₀ controls D_[8:0]
CY7C11631KV18  BWS₀ controls D_[8:0] and BWS₁ controls D_[17:9].
CY7C11651KV18  BWS₀ controls D_[8:0], BWS₁ controls D_[17:9],
ABWll tShe^{2 cBoyntetroWlsriDte[2}S⁶e^:1l⁸e^]catsndarBeWsaSm³ pcloendtroonlsthDe^[3s^5:a²m^7].e edge as the data. Deselecting a Byte Write Select
ignores the corresponding byte of data and it is not written into the device.
A
Input- Address Inputs. Sampled on the rising edge of the K clock during active read and write operations. These
Synchronous address inputs are multiplexed for both read and write operations. Internally, the device is organized as
2M x 8 (4 arrays each of 512K x 8) for CY7C11611KV18, 2M x 9 (4 arrays each of 512K x 9) for
CY7C11761KV18, 1M x 18 (4 arrays each of 256K x 18) for CY7C11631KV18 and 512K x 36 (4 arrays
each of 128K x 36) for CY7C11651KV18. Therefore, only 19 address inputs are needed to access the
entire memory array of CY7C11611KV18 and CY7C11761KV18, 18 address inputs for CY7C11631KV18
and 17 address inputs for CY7C11651KV18. These inputs are ignored when the appropriate port is
deselected.
Q_[x:0]
RPS
Outputs- Data Output Signals. These pins drive out the requested data when the read operation is active. Valid
Synchronous data is driven out on the rising edge of the K and K clocks during read operations. On deselecting the
read port, Q_[x:0] are automatically tristated.
CY7C11611KV18  Q_[7:0]
CY7C11761KV18  Q_[8:0]
CY7C11631KV18  Q_[17:0]
CY7C11651KV18  Q_[35:0]
Input- Read Port Select  Active LOW. Sampled on the rising edge of positive input clock (K). When active, a
Synchronous read operation is initiated. Deasserting deselects the read port. When deselected, the pending access is
allowed to complete and the output drivers are automatically tristated following the next rising edge of the
K clock. Each read access consists of a burst of four sequential transfers.
QVLD
Valid output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and CQ.
indicator
K
Input Clock Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device
and to drive out data through Q_[x:0]. All accesses are initiated on the rising edge of K.
K
Input Clock Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device and
to drive out data through Q_[x:0].
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+. The timings for the echo clocks are shown in the Switching Characteristics on page 24.
CQ
Echo Clock Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input clock
(K) of the QDR II+.The timings for the echo clocks are shown in the Switching Characteristics on page 24.
Document Number: 001-53197 Rev. *C
Page 7 of 29
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