CY7C1011CV33_09 Datasheet, PDF (7/13 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY7C1011CV33
Switching Waveforms
Figure 5. Read Cycle No. 1 (Address Transition Controlled)^{[10, 11]}
t_RRCC
ADDRESS
DATA OUT
t_AA
t_OHA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle No. 2 (OE Controlled)^{[11, 12]}
ADDRESS
CE
OE
BHE, BLE
DATA OUT
V_CC
SUPPLY
CURRENT
t_RC
t_ACE
t_DOE
t_LZOE
t_DBE
t_LZBE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
t_HZOE
DATA VALID
t_HZCE
t_HZBE
HIGH
IMPEDANCE
t_PD
I_CC
50%
I_SB
Notes
10. Device is continuously selected. OE, CE, BHE, and/or BLE = V_IL.
11. WE is HIGH for read cycle.
12. Address valid prior to or coincident with CE transition LOW.
Document Number: 38-05232 Rev. *H
Page 7 of 13
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