CY7C1011CV33_09 Datasheet, PDF (1/13 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY7C1011CV33
2-Mbit (128K x 16) Static RAM
Features
■ Temperature ranges
❐ Industrial: –40°C to 85°C
❐ Automotive-A: –40°C to 85°C
❐ Automotive-E: –40°C to 125°C
■ Pin and function compatible with CY7C1011BV33
■ High speed
❐ t_AA = 10 ns (Industrial and Automotive-A)
❐ t_AA = 12 ns (Automotive-E)
■ Low active power
❐ 360 mW (max) (Industrial and Automotive-A)
■ Data Retention at 2.0
■ Automatic power down when deselected
■ Independent control of upper and lower bits
■ Easy memory expansion with CE and OE features
■ Available in Pb-free 44-pin TSOP II, 44-pin TQFP and non
Pb-free 48-Ball VFBGA packages
Functional Description
The CY7C1011CV33 is a high performance CMOS static RAM
organized as 131,072 words by 16 bits. This device has an
automatic power down feature that significantly reduces power
consumption when deselected.
To write to the device, take Chip Enable (CE) and Write Enable
(WE) inputs LOW. If Byte Low Enable (BLE) is LOW, then data
from I/O pins (I/O₀ through I/O₇), is written into the location
specified on the address pins (A₀ through A₁₆). If Byte High
Enable (BHE) is LOW, then data from I/O pins (I/O₈ through
I/O₁₅) is written into the location specified on the address pins
(A₀ through A₁₆).
To read from the device, take Chip Enable (CE) and Output
Enable (OE) LOW while forcing the Write Enable (WE) HIGH. If
Byte Low Enable (BLE) is LOW, then data from the memory
location specified by the address pins appear on I/O₀ to I/O₇. If
Byte High Enable (BHE) is LOW, then data from memory
appears on I/O₈ to I/O₁₅. For more information, see the “Truth
Table” on page 9 for a complete description of Read and Write
modes.
The input and output pins (I/O₀ through I/O₁₅) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), the BHE and BLE are
disabled (BHE, BLE HIGH), or during a write operation (CE LOW
and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
INPUT BUFFER
A₀
A₁
A₂
A₃
128K x 16
A₄
A₅
RAM Array
A₆
A₇
A₈
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
BHE
WE
CE
OE
BLE
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-05232 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 23, 2009
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