CY7B9950_07 Datasheet, PDF (7/12 Pages) Cypress Semiconductor – 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer

AC Test Loads and Waveforms
Output
Figure 2. AC Test Loads
VDDQ
20 pF
Output
150Ω
150Ω
20 pF
For Lock Output
For All Other Outputs
CY7B9950
2.0V
VTH =1.5V
0.8V
t_ORISE
Figure 3. Output Waveforms
t_OFALL
t_{PW L}
t_PWH
1.7V
VTH =1.25V
0.7V
t_ORISE
t_OFALL
t_PWL
t_PWH
3.3V LVTTL OUTPUT WAVEFORM
2.5V LVTTL OUTPUT WAVEFORM
Figure 4. Test Waveforms
3.0V
2.0V
VTH =1.5V
0.8V
0V
≤ 1 ns
≤1 ns
3.3V LVTTL INPUT TEST WAVEFORM
2.5V
1.7V
VTH =1.25V
0.7V
0V
≤1 ns
≤ ^{1 ns}
2.5V LVTTL INPUT TEST WAVEFORM
AC Input Specifications
Parameter
Description
T_R,T_F
T_PWC
T_DCIN
F_REF
Input Rise/Fall Time
Input Clock Pulse
Input Duty Cycle
Reference Input
Frequency
0.8V – 2.0V
HIGH or LOW
FS = LOW
FS = MID
FS = HIGH
Condition
Min
Max
Unit
–
10
ns/V
2
–
ns
10
90
%
6
50
12
100
MHz
24
200
Document #: 38-07338 Rev. *D
Page 7 of 12
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