CY7B9950_07 Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 2.5/3.3V, 200 MHz High-Speed Multi-Phase PLL Clock Buffer

RoboClock^®, CY7B9950
2.5/3.3V, 200 MHz High-Speed
Multi-Phase PLL Clock Buffer
Features
■ 2.5V or 3.3V operation
■ Split output bank power supplies
■ Output frequency range: 6 MHz to 200 MHz
■ 50 ps typical matched-pair Output-output skew
■ 50 ps typical Cycle-cycle jitter
■ 49.5/50.5% typical output duty cycle
■ Selectable output drive strength
■ Selectable positive or negative edge synchronization
■ Eight LVTTL outputs driving 50 Ω terminated lines
■ LVCMOS/LVTTL over-voltage-tolerant reference input
■ Phase adjustments in 625-/1250-ps steps up to +7.5 ns
■ 2x, 4x multiply and (1/2)x, (1/4)x divide ratios
■ Spread-Spectrum compatible
■ Industrial temp. range: –40°C to +85°C
■ 32-pin TQFP package
Description
The CY7B9950 RoboClock^® is a low voltage, low power,
eight-output, 200 MHz clock driver. It features output phase
programmability which is necessary to optimize the timing of
high performance computer and communication systems.
The user can program the phase of the output banks through
nF[0:1] pins. The adjustable phase feature allows the user to
skew the outputs to lead or lag the reference clock. Any one
of the outputs can be connected to the feedback input to
achieve different reference frequency multiplications, and
divide ratios and zero input-output delay.
The device also features split output bank power supplies,
which enable the user to run two banks (1Qn and 2Qn) at a
power supply level different from that of the other two banks
(3Qn and 4Qn). Additionally, the three-level PE/HD pin
controls the synchronization of the output signals to either the
rising, or the falling edge of the reference clock and selects the
drive strength of the output buffers. The high drive option
(PE/HD = MID) increases the output current from ± 12 mA to
± 24 mA(3.3V).
Logic Block Diagram
TEST PE/HD FS VDDQ1
REF
FB
3
3
3
PLL
1F1:0
2F1:0
3F1:0
4F1:0
3 _Phase
3 ^Select
3 _Phase
3 ^Select
3 ^Phase
Select
3 _{and /K}
3 Phase
Select
3 and /M
1Q0
1Q1
2Q0
2Q1
3Q0
3Q1
VDDQ3
4Q0
4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-07338 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 27, 2007
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