CY62137FV30 Datasheet, PDF (7/12 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137FV30 MoBL^®
Switching Waveforms (continued)
Figure 7. Write Cycle 1: WE Controlled ^{[16, 20, 21]}
ADDRESS
CE
WE
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
BHE/BLE
OE
DATA IO
ADDRESS
CE
WE
BHE/BLE
t_BW
NOTE 22
t_HZOE
t_SD
t_HD
DATA_IN
Figure 8. Write Cycle 2: CE Controlled ^{[16, 20, 21]}
t_WC
t_SCE
t_SA
t_AW
t_HA
t_PWE
t_BW
OE
DATA IO
NOTE 22
t_HZOE
t_SD
t_HD
DATA_IN
Notes
20. Data IO is high impedance if OE = V_IH.
21. If CE goes HIGH simultaneously with WE = V_IH, the output remains in a high impedance state.
22. During this period, the IOs are in output state. Do not apply input signals.
Document Number: 001-07141 Rev. *E
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