CY62137FV30 Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137FV30 MoBL^®
Switching Waveforms
Figure 5. Read Cycle 1: Address Transition Controlled ^{[17, 18]}
t_RC
ADDRESS
DATA OUT
t_OHA
t_AA
PREVIOUS DATA VALID
DATA VALID
Figure 6. Read Cycle 2: OE Controlled ^{[18, 19]}
ADDRESS
CE
OE
BHE/BLE
DATA OUT
V_CC
SUPPLY
CURRENT
t_RC
t_ACE
t_DOE
t_LZOE
t_DBE
t_LZBE
HIGHIMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
t_PD
t_HZCE
t_HZOE
t_HZBE
HIGH
IMPEDANCE
I_CC
50%
I_SB
Notes
17. The device is continuously selected. OE, CE = V_IL, BHE and/or BLE = V_IL.
18. WE is HIGH for read cycle.
19. Address valid before or similar to CE and BHE, BLE transition LOW.
Document Number: 001-07141 Rev. *E
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