CY14MB064Q_12 Datasheet, PDF (7/30 Pages) Cypress Semiconductor – 64-Kbit (8 K × 8) SPI nvSRAM

CY14MB064Q
CY14ME064Q
Invalid Opcode
If an invalid opcode is received, the opcode is ignored and the
device ignores any additional serial data on the SI pin till the next
falling edge of CS and the SO pin remains tri-stated.
Status Register
CY14MX064Q has an 8-bit Status Register. The bits in the Status
Register are used to configure the SPI bus. These bits are
described in the Table 4 on page 10.
Figure 4. System Configuration Using SPI nvSRAM
SCK
MOSI
M IS O
uC ontroller
CS1
HOLD1
CS2
HOLD2
SCK SI
SO
CY14MX064Q
CS
HOLD
SCK SI
SO
CY14MX064Q
CS
HOLD
SPI Modes
CY14MX064Q may be driven by a microcontroller with its SPI
peripheral running in either of the following two modes:
■ SPI Mode 0 (CPOL=0, CPHA=0)
■ SPI Mode 3 (CPOL=1, CPHA=1)
For both these modes, the input data is latched in on the rising
edge of SCK starting from the first rising edge after CS goes
active. If the clock starts from a HIGH state (in mode 3), the first
rising edge after the clock toggles, is considered. The output data
is available on the falling edge of SCK.
The two SPI modes are shown in Figure 5 and Figure 6. The
status of clock when the bus master is in standby mode and not
transferring data is:
■ SCK remains at 0 for Mode 0
■ SCK remains at 1 for Mode 3
CPOL and CPHA bits must be set in the SPI controller for either
Mode 0 or Mode 3. The device detects the SPI mode from the
status of SCK pin when the device is selected by bringing the CS
pin LOW. If SCK pin is LOW when the device is selected, SPI
Mode 0 is assumed and if SCK pin is HIGH, it works in SPI
Mode 3.
CS
SCK
SI
Figure 5. SPI Mode 0
012 345 67
7 654321 0
MSB
LSB
Figure 6. SPI Mode 3
CS
SCK
012 34567
SI
7 654321 0
MSB
LSB
Document Number: 001-65018 Rev. *D
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