CY14E256LA_11 Datasheet, PDF (7/19 Pages) Cypress Semiconductor – 256-Kbit (32 K × 8) Nonvolatile SRAM

CY14E256LA
Best Practices
nvSRAM products have been used effectively for over 27 years.
While ease-of-use is one of the product’s main system values,
experience gained working with hundreds of applications has
resulted in the following suggestions as best practices:
■ The nonvolatile cells in this nvSRAM product are delivered from
Cypress with 0x00 written in all cells. Incoming inspection
routines at customer or contract manufacturer’s sites
sometimes reprogram these values. Final NV patterns are
typically repeating patterns of AA, 55, 00, FF, A5, or 5A. End
product’s firmware should not assume an NV array is in a set
programmed state. Routines that check memory content
values to determine first time system configuration, cold or
warm boot status, and so on should always program a unique
NV pattern (that is, complex 4-byte pattern of 46 E6 49 53 hex
or more random bytes) as part of the final system manufac-
turing test to ensure these system routines work consistently.
■ Power-up boot firmware routines should rewrite the nvSRAM
into the desired state (for example, AutoStore enabled). While
the nvSRAM is shipped in a preset state, best practice is to
again rewrite the nvSRAM into the desired state as a safeguard
against events that might flip the bit inadvertently such as
program bugs and incoming inspection routines.
■ The V_CAP value specified in this data sheet includes a minimum
and a maximum value size. Best practice is to meet this
requirement and not exceed the maximum V_CAP value because
the nvSRAM internal algorithm calculates V_CAP charge and
discharge time based on this maximum V_CAP value. Customers
that want to use a larger V_CAP value to make sure there is extra
store charge and store time should discuss their V_CAP size
selection with Cypress to understand any impact on the V_CAP
voltage level at the end of a t_RECALL period.
Document Number: 001-54952 Rev. *F
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