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W159 Datasheet, PDF (6/11 Pages) Cypress Semiconductor – Spread Spectrum System FTG for SMP Systems
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W159
DC Electrical Characteristics: TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V±5% (continued)
Parameter
Description
Test Condition
Min.
Typ.
Max.
Unit
Crystal Oscillator
VTH
X1 Input Threshold Voltage[14]
CLOAD
Load Capacitance, Imposed on
External Crystal[15]
CIN,X1
X1 Input Capacitance[16]
Pin Capacitance/Inductance
Pin X2 unconnected
1.65
V
18
pF
28
pF
CIN
COUT
LIN
Input Pin Capacitance
Output Pin Capacitance
Input Pin Inductance
Except X1 and X2
5
pF
6
pF
7
nH
3.3V AC Electrical Characteristics
TA = 0°C to +70°C, VDDQ3 = 3.3V±5%, VDDQ2 = 2.5V± 5%, fXTL = 14.31818 MHz
Spread Spectrum function turned off
AC clock parameters are tested and guaranteed over stated operating conditions using the stated lump capacitive load at the
clock output.[17]
3V66 Clock Outputs, 3V66_0:3 (Lump Capacitance Test Load = 30 pF)
Parameter
Description
Test Condition/Comments
Min. Typ. Max. Unit
f
Frequency
Note 18
66.6
MHz
tH
High Time
Duration of clock cycle above 2.4V
4.95
tL
Low Time
Duration of clock cycle below 0.4V
4.55
tR
Output Rise Edge Rate Measured from 0.4V to 2.4V
1
tF
Output Fall Edge Rate Measured from 2.4V to 0.4V
1
tD
Duty Cycle
Measured on rising and falling edge at 1.5V
45
tJC
Jitter, Cycle-to-Cycle
Measured on rising edge at 1.5V. Maximum dif-
ference of cycle time between two adjacent
cycles.
ns
ns
4
V/ns
4
V/ns
55
%
500
ps
tSK
Output Skew
Measured on rising edge at 1.5V
tO
CPU to 3V66 Clock Skew Covers all 3V66 outputs. Measured on rising
0
edge at 1.5V. CPU leads 3V66 outputs.
250
ps
1.5
ns
fST
Frequency Stabilization Assumes full supply voltage reached within
from Power-up (cold start) 1 ms from power-up. Short cycles exist prior to
frequency stabilization.
3
ms
Zo
AC Output Impedance Average value during switching transition.
15
Ω
Used for determining series termination value.
Notes:
14. X1 input threshold voltage (typical) is VDD/2.
15. The W159 contains an internal crystal load capacitor between pin X1 and ground and another between pin X2 and ground. Total load placed on crystal is 18 pF;
this includes typical stray capacitance of short PCB traces to crystal.
16. X1 input capacitance is applicable when driving X1 with an external clock source (X2 is left unconnected).
17. Period, jitter, offset, and skew measured on rising edge at 1.5V.
18. 3V66 is CPU/2 for CPU =133 MHz and (2 x CPU)/3 for CPU = 100 MHz.
Document #: 38-07163 Rev. *A
Page 6 of 11
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