W130 Datasheet, PDF (6/8 Pages) Cypress Semiconductor – Spread Spectrum Desktop/Notebook System Clock

PRELIMINARY
W130
PCI Clock Outputs, PCI1:7 and PCI_F (Lump Capacitance Test Load = 30 pF
Parameter
Description
t_P
Period
t_H
High Time
t_L
Low Time
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
t_JC
Jitter, Cycle-to-Cycle
t_SK
Output Skew
t_O
CPU to PCI Clock Skew
f_ST
Frequency Stabilization
from Power-up (cold
start)
Z_o
AC Output Impedance
Test Condition/Comments
Measured on rising edge at 1.5V
Duration of clock cycle above 2.4V
Duration of clock cycle below 0.4V
Measured from 0.4V to 2.4V
Measured from 2.4V to 0.4V
Measured on rising and falling edge at 1.5V
Measured on rising edge at 1.5V. Maximum
difference of cycle time between two adjacent cycles.
Measured on rising edge at 1.5V
Covers all CPU/PCI outputs. Measured on rising
edge at 1.5V. CPU leads PCI output.
Assumes full supply voltage reached within 1 ms
from power-up. Short cycles exist prior to frequency
stabilization.
Average value during switching transition. Used for
determining series termination value.
CPU = 66.6/100 MHz
Min. Typ. Max.
30
12
12
1
4
1
4
45
55
250
500
1.5
4
3
30
Unit
ns
ns
ns
V/ns
V/ns
%
ps
ps
ns
ms
Ω
APIC0:1 Clock Output (Lump Capacitance Test Load = 20 pF)
Parameter
Description
f
Frequency, Actual
t_R
Output Rise Edge Rate
t_F
Output Fall Edge Rate
t_D
Duty Cycle
f_ST
Frequency Stabilization
from Power-up (cold start)
Z_o
AC Output Impedance
Test Condition/Comments
Frequency generated by crystal oscillator
Measured from 0.4V to 2.0V
Measured from 2.0V to 0.4V
Measured on rising and falling edge at 1.25V
Assumes full supply voltage reached within
1 ms from power-up. Short cycles exist prior to
frequency stabilization.
Average value during switching transition.
Used for determining series termination value.
CPU = 66.6/100MHz
Min. Typ. Max.
14.31818
1
4
1
4
45
55
1.5
15
Unit
MHz
V/ns
V/ns
%
ms
Ω
REF0:2 Clock Output (Lump Capacitance Test Load = 20 pF)
CPU = 66.6/100 MHz
Parameter
Description
Test Condition/Comments
Min. Typ. Max.
f
Frequency, Actual
Frequency generated by crystal oscillator
14.318
t_R
Output Rise Edge Rate
Measured from 0.4V to 2.4V
0.5
2
t_F
Output Fall Edge Rate
Measured from 2.4V to 0.4V
0.5
2
t_D
Duty Cycle
Measured on rising and falling edge at 1.5V
45
55
f_ST
Frequency Stabilization from Assumes full supply voltage reached within 1 ms
3
Power-up (cold start)
from power-up. Short cycles exist prior to
frequency stabilization.
Z_o
AC Output Impedance
Average value during switching transition. Used for
40
determining series termination value.
Unit
MHz
V/ns
V/ns
%
ms
Ω
6