PALCE22V10 Datasheet, PDF (6/13 Pages) Lattice Semiconductor – 24-Pin EE CMOS (Zero Power) Versatile PAL Device

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PALCE22V10
Commercial Switching Characteristics PALCE22V10 (continued)^{[2, 7]}
22V10-5
22V10-7 22V10-10
Parameter
Description
Min. Max. Min. Max. Min. Max.
t_S1
Input or Feedback Set-Up Time 3
5
6
t_S2
Synchronous Preset Set-Up
4
6
7
Time
t_H
t_P
t_WH
t_WL
f_MAX1
f_MAX2
f_MAX3
t_CF
Input Hold Time
0
0
0
External Clock Period (t_CO + t_S) 7
10
12
Clock Width HIGH^[6]
2.5
3
3
Clock Width LOW^[6]
2.5
3
3
External Maximum
143
100
76.9
Frequency (1/(t_CO + t_S))^[11]
Data Path Maximum Frequency 200
166
142
(1/(t_WH + t_WL))^{[6, 12]}
Internal Feedback Maximum
181
133
111
Frequency (1/(t_CF + t_S))^[6,13]
Register Clock to
Feedback Input^[6,14]
2.5
2.5
3
t_AW
Asynchronous Reset Width
8
t_AR
Asynchronous Reset
4
Recovery Time
8
10
5
6
t_AP
Asynchronous Reset to
Registered Output Delay
7.5
12
13
t_SPR
Synchronous Preset
Recovery Time
4
6
8
t_PR
Power-up Reset Time^[6,15]
1
1
1
Military and Industrial Switching Characteristics PALCE22V10 ^{[2, 7]}
22V10-15
Min. Max.
10
10
0
20
6
6
55.5
83.3
68.9
4.5
15
10
20
10
1
22V10-25
Min. Max.
15
15
0
30
13
13
33.3
35.7
38.5
13
25
25
25
15
1
Unit
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
ns
ns
ns
ns
µs
22V10-10
22V10-15
22V10-25
Parameter
Description
Min. Max. Min. Max. Min. Max.
Unit
t_PD
Input to Output
Propagation Delay^[8]
3
10
3
15
3
25
ns
t_EA
Input to Output Enable Delay^[9]
10
15
25
ns
t_ER
Input to Output Disable Delay^[10]
10
15
25
ns
t_CO
Clock to Output Delay^[8]
2
7
2
8
2
15
ns
t_S1
Input or Feedback Set-up Time
6
10
18
ns
t_S2
Synchronous Preset Set-up Time 7
10
18
ns
t_H
Input Hold Time
0
0
0
ns
t_P
External Clock Period (t_CO + t_S)
12
20
33
ns
t_WH
Clock Width HIGH^[6]
3
6
14
ns
t_WL
Clock Width LOW^[6]
3
6
14
ns
f_MAX1
External Maximum Frequency
(1/(t_CO + t_S))^[11]
76.9
50.0
30.3
MHz
f_MAX2
Data Path Maximum Frequency 142
(1/(t_WH + t_WL))^{[6, 12 ]}
83.3
35.7
MHz
Notes:
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f_MAX internal (1/f_MAX3) as measured (see Note above) minus t_S.
15. The registers in the PALCE22V10 have been designed with the capability to reset during system power-up. Following power-up, all registers will be reset to a
logic LOW state. The output state will depend on the polarity of the output buffer. This feature is useful in establishing state machine initialization. To insure proper
operation, the rise in V_CC must be monotonic and the timing constraints depicted in Power-Up Reset Waveform must be satisfied.
Document #: 38-03027 Rev. *B
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