PALCE20V8_04 Datasheet, PDF (6/14 Pages) Cypress Semiconductor – Flash-Erasable Reprogrammable CMOS PAL® Device

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PALCE20V8
Commercial and Industrial Switching Characteristics (continued)^[3]
20V8−5
Parameter
Description
Min.
t_WH
Clock Width HIGH^[8]
3
t_WL
Clock Width LOW^[8]
3
f_MAX1
External Maximum
143
Frequency (1/(t_CO + t_S))^[8,11]
f_MAX2
Data Path Maximum
166.6
Frequency (1/(t_WH + t_WL))^{[8, 12]}
f_MAX3
Internal Feedback Maximum 166.6
Frequency (1/(t_CF + t_S))^[8,13]
t_CF
Register Clock to
Feedback Input^{[8, 14]}
t_PR
Power-Up Reset Time^[8]
1
Max.
3
20V8−7
Min. Max.
5
5
83
100
100
3
1
20V8−10
Min. Max.
8
8
58
62.5
62.5
6
1
20V8−15
Min. Max.
8
8
45.5
62.5
50
8
1
20V8−25
Min. Max.
12
12
37
41.6
40
10
1
Unit
ns
ns
MHz
MHz
MHz
ns
µs
Military Switching Characteristics^[3]
Parameter
t_PD
t_PZX
t_PXZ
t_EA
t_ER
t_CO
t_S
t_H
t_P
t_WH
t_WL
f_MAX1
f_MAX2
f_MAX3
t_CF
t_PR
Description
Input to Output Propagation Delay^[9]
OE to Output Enable
OE to Output Disable
Input to Output Enable Delay^[8]
Input to Output Disable Delay^[8,10]
Clock to Output Delay^[9]
Input or Feedback Set-Up Time
Input Hold Time
External Clock Period (t_CO + t_S)
Clock Width HIGH^[8]
Clock Width LOW^[8]
External Maximum Frequency
(1/(t_CO + t_S)^[8,11]
Data Path Maximum Frequency
(1/(t_WH + t_WL))^{[8, 12 ]}
Internal Feedback Maximum
Frequency (1/(t_CF + t_S))^[8,13]
Register Clock to
Feedback Input^{[8, 14]}
Power-Up Reset Time^[8]
20V8−10
Min. Max.
1
10
10
10
10
10
1
10
10
0
20
8
8
50
62.5
62.5
6
1
20V8−15
Min. Max.
1
15
15
15
15
15
1
12
12
0
24
10
10
41.7
50
50
8
1
20V8−25
Min. Max.
1
25
20
20
25
25
1
20
20
0
40
15
15
25
33.3
33.3
10
1
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
MHz
MHz
MHz
ns
µs
Document #: 38-03026 Rev. *B
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