PALCE20V8_04 Datasheet, PDF (5/14 Pages) Cypress Semiconductor – Flash-Erasable Reprogrammable CMOS PAL® Device

USE ULTRA37000^TM FOR
ALL NEW DESIGNS
AC Test Loads and Waveforms
3.0V
GND
≤ 2 ns
ALL INPUT PULSES
90%
10%
90%
10%
≤ 2 ns
PALCE20V8
5V
OUTPUT
S1
R1
TEST POINT
R2
C_L
Specification
t_PD, t_CO
t_PZX, t_EA
t_PXZ, t_ER
S₁
Closed
Z ⎜ H: Open
Z ⎜ L: Closed
H ⎜ Z: Open
L ⎜ Z: Closed
C_L
50 pF
5 pF
Commercial
R₁
200Ω
R₂
390Ω
Military
R₁
390Ω
R₂
750Ω
Measured Output Value
1.5V
1.5V
H ⎜ Z: V_OH − 0.5V
L ⎜ Z: V_OL + 0.5V
Commercial and Industrial Switching Characteristics ^[3]
20V8−5
20V8−7
20V8−10
20V8−15
20V8−25
Parameter
Description
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Unit
t_PD
Input to Output
Propagation Delay^[9]
1
5
1 7.5 1 10 1 15 1 25 ns
t_PZX
OE to Output Enable
t_PXZ
OE to Output Disable
t_EA
Input to Output Enable
Delay^[8]
5
6
10
15
20 ns
5
6
10
15
20 ns
6
9
10
15
25 ns
t_ER
Input to Output
Disable Delay^[8,10]
6
9
10
15
25 ns
t_CO
Clock to Output Delay^[9]
1
4
1
5
1
7
1 10 1 12 ns
t_S
Input or Feedback Set-up
3
Time
7
10
12
15
ns
t_H
Input Hold Time
0
0
0
0
0
ns
t_P
External Clock Period
7
(t_CO + t_S)
12
17
22
27
ns
Shaded areas contain preliminary information.
Notes:
9. Min. times are tested initially and after any design or process changes that may affect these parameters.
10. This parameter is measured as the time after OE pin or internal disable input disables or enables the output pin. This delay is measured to the point at which a previous HIGH
level has fallen to 0.5 volts below V_OH min. or a previous LOW level has risen to 0.5 volts above V_OL max.
11. This specification indicates the guaranteed maximum frequency at which a state machine configuration with external feedback can operate.
12. This specification indicates the guaranteed maximum frequency at which the device can operate in data path mode.
13. This specification indicates the guaranteed maximum frequency at which a state machine configuration with internal only feedback can operate.
14. This parameter is calculated from the clock period at f_MAX internal (1/f_MAX3) as measured (see Note 7 above) minus t_S.
Document #: 38-03026 Rev. *B
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