CYW20702 Datasheet, PDF (6/55 Pages) Cypress Semiconductor – Bluetooth 4.0 + EDR and Low Energy compliant

1.2 Block Diagram
Figure 2 shows the interconnect of the major CYW20702 physical blocks and associated external interfaces.
Figure 2. Functional Block Diagram
JTAG
Flash I/F
RF
ARM7TDMI‐S
DMA
Address Decoder
AHB2EBI
External
Bus I/F
Trap & Patch
32‐bit AHB
AHB2APB
AHB2MEM
AHB2MEM
PMU Control
WD Timer
GPIO+Aux
Remap &
Pause
SW
Timers
ROM
RAM
Interrupt
Controller
JTAG Master
OTP
(128 bytes)
32‐bit APB
Bluetooth Radio
Blue RF Registers
Digital
Modulator
Calibration &
Control
Digital Demod
Bit Sync
Low Power
Scan
LCU
Buffer
APU
Blue RF I/F
BT Clk/
Hopper
Rx/Tx
Buffer
PMU
LPO
POR
COEX
SECI
Bus Arb
Scan JTAG
SPI
Master
USB
PCM
UART
Debug UART
SPI Transport
I2C_Master
FIFO 1
FIFO 2
PTU
CYW20702
I/O
Port Control
Digital I/O
Document Number: 002-14773 Rev. *L
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