CYU01M16SCE Datasheet, PDF (6/11 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Pseudo Static RAM

PRELIMINARY
Switching Waveforms
Read Cycle 1 (Address Transition Controlled)^{[17, 18]}
t_RC
ADDRESS
DATA OUT
t_OHA
t_AA
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)^{[16, 18, 19]}
ADDRESS
t_RC
CE₁
t_CD
CE₂
CYU01M16SCE
MoBL3™
DATA VALID
t_HZCE
BHE/BLE
t_ACE
OE
DATA OUT
VCC
SUPPLY
CURRENT
t_LZBE
t_DBE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
50%
t_HZBE
t_HZOE
DATA VALID
50%
Notes:
16. Whenever CE₁ = HIGH or CE₂ = LOW, BHE/BLE are taken inactive, they must remain inactive for a minimum of 5 ns.
17. Device is continuously selected. OE = CE₁ = V_IL and CE₂ = V_IH.
18. WE is HIGH for Read Cycle.
19. CE is the Logical AND of CE₁ and CE₂.
IMPEDANCE
HIGH
I_CC
I_SB
Document #: 38-05601 Rev. *D
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