CYU01M16SCE Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Pseudo Static RAM

PRELIMINARY
CYU01M16SCE
MoBL3™
16-Mbit (1M x 16) Pseudo Static RAM
Features
• Wide voltage range: 2.2V–3.6V
• Access Time: 70 ns
• Ultra-low active power
— Typical active current: 3 mA @ f = 1 MHz
— Typical active current: 18 mA @ f = f_max
• Ultra low standby power
• Automatic power-down when deselected
• CMOS for optimum speed/power
• Offered in a 48-ball BGA Package
• Operating Temperature: –40°C to +85°C
Functional Description^[1]
The CYU01M16SCE is a high-performance CMOS Pseudo
Static RAM organized as 1M words by 16 bits that supports an
asynchronous memory interface. This device features
advanced circuit design to provide ultra-low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
Logic Block Diagram
DATA IN DRIVERS
portable applications such as cellular telephones. The device
can be put into standby mode when deselected (CE₁ HIGH or
CE₂ LOW or both BHE and BLE are HIGH). The input/output
pins (I/O₀ through I/O₁₅) are placed in a high-impedance state
when: deselected (CE₁ HIGH or CE₂ LOW), outputs are
disabled (OE HIGH), both Byte High Enable and Byte Low
Enable are disabled (BHE, BLE HIGH), or during a write
operation (CE₁ LOW and CE₂ HIGH and WE LOW).
To write to the device, take Chip Enable (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If Byte Low Enable
(BLE) is LOW, then data from I/O pins (I/O₀ through I/O₇), is
written into the location specified on the address pins (A₀
through A₁₉). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₉).
To read from the device, take Chip Enables (CE₁ LOW and
CE₂ HIGH) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins will appear on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory will appear on I/O₈ to I/O₁₅.
Refer to the truth table for a complete description of read and
write modes.
A₈
A₉
A₁₀
A₁₁
A₁₂
1M x 16
A₁₃
A₁₄
RAM Array
A₁₅
A₁₆
A₁₇
A₁₈
A₁₉
I/O₀–I/O₇
I/O₈–I/O₁₅
COLUMN DECODER
Power -Down
Circuit
BHE
BLE
BHE
WE
OE
BLE
CE₂
CE₁
CE₂
CE₁
Note:
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document #: 38-05601 Rev. *D
Revised August 7, 2006