CY7C185D Datasheet, PDF (6/10 Pages) Cypress Semiconductor – 64K (8K x 8) Static RAM

Switching Waveforms (continued)
Read Cycle No.2^[13,14]
CE₁
PRELIMINARY
t_RC
CY7C185D
CE₂
OOEE
t_ACE
DATA OUT
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
V_CC
SUPPLY
CURRENT
t_PU
50%
Write Cycle No. 1 (WE Controlled)^[12,14]
ADDRESS
DATA VALID
t_WC
CE₁
CCEE₂
WE
t_SCEI
t_AW
t_SCE2
t_SA
t_PWE
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
ICC
50%
ISB
t_HA
OE
DATA I/O
NOTE 15
t_HZOE
Write Cycle No. 2 (CE Controlled)^[14,15,16]
ADDRESS
CE₁
t_SA
CE₂
t_SD
DATA _IN VALID
t_WC
t_AW
t_SCE1
t_SCE2
t_HD
t_HA
WE
t_SD
t_HD
DATA I/O
DATA _IN VALID
Notes:
13. Data I/O is High Z if OE = V_IH, CE₁ = V_IH, WE = V_IL, or CE₂=V_IL.
14. The internal write time of the memory is defined by the overlap of CE₁ LOW, CE₂ HIGH and WE LOW. CE₁ and WE must be LOW and CE₂ must be HIGH to
initiate write. A write can be terminated by CE₁ or WE going HIGH or CE₂ going LOW. The data input set-up and hold timing should be referenced to the rising
edge of the signal that terminates the write.
15. During this period, the I/Os are in the output state and input signals should not be applied.
16. The minimum write cycle time for write cycle #3 (WE controlled, OE LOW) is the sum of t_HZWE and t_SD.
Document #: 38-05466 Rev. *C
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