CY7C185D Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 64K (8K x 8) Static RAM

PRELIMINARY
CY7C185D
64K (8K x 8) Static RAM
Features
• Pin- and function-compatible with CY7C185
• High speed
— t_AA = 10 ns
• Low active power
— I_CC = 60 mA @ 10 ns
• Low CMOS standby power
— I_SB2 = 3 mA
• CMOS for optimum speed/power
• Data Retention at 2.0V
• Easy memory expansion with CE₁, CE₂, and OE features
• TTL-compatible inputs and outputs
• Automatic power-down when deselected
• Available in Lead (Pb)-Free Packages
Functional Description^[1]
The CY7C185D is a high-performance CMOS static RAM
organized as 8192 words by 8 bits. Easy memory expansion
is provided by an active LOW chip enable (CE₁), an active
HIGH chip enable (CE₂), and active LOW output enable (OE)
and three-state drivers. This device has an automatic
power-down feature (CE₁ or CE₂), reducing the power
consumption when deselected.
An active LOW write enable signal (WE) controls the
writing/reading operation of the memory. When CE₁ and WE
inputs are both LOW and CE₂ is HIGH, data on the eight data
input/output pins (I/O₀ through I/O₇) is written into the memory
location addressed by the address present on the address
pins (A₀ through A₁₂). Reading the device is accomplished by
selecting the device and enabling the outputs, CE₁ and OE
active LOW, CE₂ active HIGH, while WE remains inactive or
HIGH. Under these conditions, the contents of the location
addressed by the information on address pins are present on
the eight data input/output pins.
The input/output pins remain in a high-impedance state unless
the chip is selected, outputs are enabled, and write enable
(WE) is HIGH.The CY7C185D is in a standard 28-pin
300-mil-wide DIP, SOJ, or SOIC Pb-Free package.
Logic Block Diagram
A₁
A₂
A₃
A₄
A₅
A₆
A₇
A₈
CE₁
CE₂
WE
OE
INPUT BUFFER
256 x 32 x 8
ARRAY
POWER
COLUMN DECODER ^DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Pin Configurations
DIP/SOJ/SOIC
Top View
NC ₁
A_{4 2}
A_{5 3}
A_{6 4}
A_{7 5}
A_{8 6}
A_{9 7}
A_{10 8}
A_{11 9}
A_{12 10}
I/O_{0 11}
I/O_{1 12}
I/O_{2 13}
GND ₁₄
28 ^VCC
27 ^WE
26 ^CE2
25 ^A3
24 ^A2
23 ^A1
22 ^OE
21 ^A0
20 ^CE1
19 ^I/O7
18 ^I/O6
17 ^I/O5
16 ^I/O4
15 ^I/O3
Note:
1. For guidelines on SRAM system design, please refer to the ‘System Design Guidelines’ Cypress application note, available on the internet at www.cypress.com.
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-05466 Rev. *C
Revised January 10, 2005