CY62167DV18_07 Datasheet, PDF (6/11 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Static RAM

Switching Waveforms
Read Cycle 1 (Address Transition Controlled)^{[14, 15]}
t_RRCC
ADDRESS
t_AA
t_OHA
DATA OUT
PREVIOUS DATA VALID
Read Cycle 2 (OE Controlled)^{[15, 16]}
CY62167DV18 MoBL^®
DATA VALID
ADDRESS
CE₁
CE₂
BHE/BLE
OE
DATA OUT
V_CC
SUPPLY
CURRENT
t_RC
t_ACE
t_LZBE
t_DBE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
t_PD
t_HZCE
t_HZBE
t_HZOE
DATA VALID
HIGH
IMPEDANCE
I_CC
50%
I_SB
Notes
14. The device is continuously selected. OE, CE₁ = V_IL, BHE and/or BLE = V_IL, and CE₂ = V_IH.
15. WE is HIGH for read cycle.
16. Address valid before or similar to CE₁, BHE, BLE transition LOW and CE₂ transition HIGH.
Document #: 38-05326 Rev. *C
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