CY62167DV18_07 Datasheet, PDF (1/11 Pages) Cypress Semiconductor – 16-Mbit (1M x 16) Static RAM

CY62167DV18 MoBL^®
16-Mbit (1M x 16) Static RAM
Features
• Very high speed: 55 ns
• Wide voltage range: 1.65V–1.95V
• Ultra low active power
— Typical active current: 1.5 mA @ f = 1 MHz
— Typical active current: 15 mA @ f = f_max
• Ultra low standby power
• Easy memory expansion with CE₁, CE₂, and OE features
• Automatic power down when deselected
• CMOS for optimum speed and power
• Available in Pb-free 48-ball VFBGA package
Functional Description^[1]
The CY62167DV18 is a high performance CMOS static RAM
organized as 1M words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 99% when addresses are not
toggling. Placing the device into standby mode reduces power
Logic Block Diagram
consumption by more than 99% when deselected (CE₁ HIGH
or CE₂ LOW or both BHE and BLE are HIGH). The input and
output pins (IO₀ through IO₁₅) are placed in a high impedance
state when:
• Deselected (CE₁ HIGH or CE₂ LOW)
• Outputs are disabled (OE HIGH)
• Both Byte High Enable (BHE) and Byte Low Enable (BLE)
are disabled (BHE, BLE HIGH)
• Write operation is active (CE₁ LOW, CE₂ HIGH and WE
LOW)
To write to the device, take Chip Enables (CE₁ LOW and CE₂
HIGH) and Write Enable (WE) input LOW. If BLE is LOW, then
data from IO pins (IO₀ through IO₇) is written into the location
specified on the address pins (A₀ through A₁₉). If BHE is LOW
then data from IO pins (IO₈ through IO₁₅) is written into the
location specified on the address pins (A₀ through A₁₉).
To read from the device, take Chip Enables (CE₁ LOW and
CE₂ HIGH) and OE LOW while forcing the WE HIGH. If BLE
is LOW, then data from the memory location specified by the
address pins appear on IO₀ to IO₇. If BHE is LOW, then data
from memory appears on IO₈ to IO₁₅. See the “Truth Table” on
page 9 for a complete description of read and write modes.
DATA IN DRIVERS
A₁₀
A₉
A₈
A₇
A₆
1M × 16
A₅
RAM Array
A₄
A₃
A₂
A
A
1
0
IO₀–IO₇
IO₈–IO₁₅
Power Down
Circuit
COLUMN DECODER
BHE
CE₂
BLE
CE₁
BYTE
BHE
WE
CE₂
CE₁
OE
BLE
Note
1. For best practice recommendations, refer to the Cypress application note “System Design Guidelines” at http://www.cypress.com.
Cypress Semiconductor Corporation
Document #: 38-05326 Rev. *C
• 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Revised April 25, 2007