CY62148VN Datasheet, PDF (6/10 Pages) Cypress Semiconductor – 4 Mbit (512K x 8) Static RAM

CY62148VN MoBL^®
Switching Waveforms
Figure 4. Read Cycle No. 1: Address Transition Controlled ^{[10, 11]}
t_RRCC
ADDRESS
t_AA
t_OHA
DATA OUT
PREVIOUS DATA VALID
DATA VALID
CE
OE
DATA OUT
SUPVP^CL^CY
CURRENT
ADDRESS
CE
WE
Figure 5. Read Cycle No. 2: OE Controlled ^{[11, 12]}
t_RC
t_ACE
t_DOE
t_LZOE
HIGH IMPEDANCE
t_LZCE
t_PU
50%
DATA VALID
Figure 6. Write Cycle No 1: WE Controlled ^{[8, 13, 14]}
t_WC
t_HZOE
t_HZCE
HIGH
IMPEDANCE
t_PD
I_CC
50%
I_SB
t_AW
t_HA
t_SA
t_PWE
OE
DATA I/O
NOTE 15
t_HZOE
t_SD
t_HD
DATA_IN VALID
Notes
10. The device is continuously selected. OE, CE = V_IL.
11. WE is HIGH for read cycle.
12. Address valid before or similar to CE transition LOW.
13. Data I/O is high impedance if OE = V_IH.
14. If CE goes HIGH simultaneously with WE = V_IH, the output remains in a high impedance state.
Document Number : 001-55636 Rev. *A
Page 6 of 10
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