CY62148VN Datasheet, PDF (1/10 Pages) Cypress Semiconductor – 4 Mbit (512K x 8) Static RAM

CY62148VN MoBL^®
4 Mbit (512K x 8) Static RAM
Features
■ Wide Voltage Range: 2.7V to 3.6V
■ Ultra Low Active Power
■ Low Standby Power
■ TTL-compatible Inputs and Outputs
■ Automatic Power Down when deselected
■ CMOS for optimum Speed and Power
■ Package available in a 32-Pin TSOP II and a 32-Pin SOIC
Package
Functional Description
The CY62148VN is a high performance CMOS static RAM
organized as 512K words by eight bits. This device features
advanced circuit design to provide ultra-low active current. This
is ideal for providing More Battery Life (MoBL^) in portable
applications such as cellular telephones. The device also has an
automatic power down feature that significantly reduces power
consumption by 99 percent when addresses are not toggling.
The device can be put into standby mode when deselected (CE
HIGH).
Writing to the device is accomplished by taking Chip Enable (CE)
and Write Enable (WE) inputs LOW. Data on the eight I/O pins
(I/O₀ through I/O₇) is then written into the location specified on
the address pins (A₀ through A₁₈).
Reading from the device is accomplished by taking Chip Enable
(CE) and Output Enable (OE) LOW while forcing Write Enable
(WE) HIGH. Under these conditions, the contents of the memory
location specified by the address pins appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high impedance state when the device is deselected (CE HIGH),
the outputs are disabled (OE HIGH), or during a write operation
(CE LOW and WE LOW).
For best practice recommendations, refer to the Cypress
application note AN1064, SRAM System Guidelines.
Logic Block Diagram
AAAAAAAAAA_1234567809
CE
WE
OE
Data in Drivers
512K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O₀
I/O₁
I/O₂
I/O₃
I/O₄
I/O₅
I/O₆
I/O₇
Cypress Semiconductor Corporation • 198 Champion Court
Document Number : 001-55636 Rev. *A
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 6, 2010
[+] Feedback