CY62137EV30_11 Datasheet, PDF (6/15 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

Switching Characteristics
Over the Operating Range
Parameter^{[15, 16]}
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
t_DBE
t_LZBE
t_HZBE
Write Cycle^[19]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_BW
t_SD
t_HD
t_HZWE
t_LZWE
Description
Read cycle time
Address to data valid
Data hold from address change
CE LOW to data valid
OE LOW to data valid
OE LOW to LOW Z^[17]
OE HIGH to High Z^{[17, 18]}
CE LOW to Low Z^[17]
CE HIGH to High Z^{[17, 18]}
CE LOW to power-up
CE HIGH to power-down
BLE/BHE LOW to data valid
BLE/BHE LOW to Low Z^[17]
BLE/BHE HIGH to HIGH Z^{[17, 18]}
Write cycle time
CE LOW to write end
Address setup to write end
Address hold from write end
Address setup to write start
WE pulse width
BLE/BHE LOW to write end
Data setup to write end
Data hold from write end
WE LOW to High-Z^{[17, 18]}
WE HIGH to Low-Z^[17]
CY62137EV30 MoBL^®
45 ns
Unit
Min
Max
45
–
ns
–
45
ns
10
–
ns
–
45
ns
–
22
ns
5
–
ns
–
18
ns
10
–
ns
–
18
ns
0
–
ns
–
45
ns
–
45
ns
5
–
ns
–
18
ns
45
–
ns
35
–
ns
35
–
ns
0
–
ns
0
–
ns
35
–
ns
35
–
ns
25
–
ns
0
–
ns
–
18
ns
10
–
ns
Notes
15.
Test conditions for all parameters other than tri-state parameters assume signal transition time
levels of 0 to V_CC(typ.), and output loading of the specified I_OL/I_OH as shown in AC Test Loads
of 3
and
ns (1V/ns) or
Waveforms.
less,
timing
reference
levels
of
V_CC(typ)/2,
input
pulse
16. AC timing parameters are subject to byte enable signals (BHE or BLE) not switching when chip is disabled. Refer application note, AN13842 for more information.
17.
At any given
device.
temperature
and
voltage
condition,
t_HZCE
is
less
than
t_LZCE,
t_HZBE
is
less
than
t_LZBE,
t_HZOE
is
less
than
t_LZOE,
and
t_HZWE
is
less
than
t_LZWE
for
any
given
18. t_HZOE, t_HZCE, t_HZBE, and t_HZWE transitions are measured when the outputs enter a high impedance state.
19.
The internal write time of the
signals can terminate a write
memory is defined by the
by going INACTIVE. The
overlap of
data input
WE, CE =
setup and
hVo^ILld, ^{BtiHmEinagnsdhoBuLlEd}
b=eVr^Ie^L.feArlel nscigendatlos
must be ACTIVE to initiate
the edge of the signal that
a write and any of these
terminates the write.
Document #: 38-05443 Rev. *D
Page 6 of 15
[+] Feedback