CY62137EV30_11 Datasheet, PDF (1/15 Pages) Cypress Semiconductor – 2-Mbit (128K x 16) Static RAM

CY62137EV30 MoBL^®
2-Mbit (128K x 16) Static RAM
Features
Functional Description
■ Very high speed: 45 ns
■ Wide voltage range: 2.20 V to 3.60 V
■ Pin compatible with CY62137CV30
■ Ultra low standby power
❐ Typical standby current: 1 A
❐ Maximum standby current: 7 A
■ Ultra low active power
❐ Typical active current: 2 mA at f = 1 MHz
■ Easy memory expansion with CE and OE features
■ Automatic power-down when deselected
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed and power
■ Byte power-down feature
■ Offered in Pb-free 48-ball very fine ball grid array (VFBGA)
and 44-pin thin small outline package (TSOPII) package
The CY62137EV30^[1] is a high performance CMOS static RAM
organized as 128K words by 16 bits. This device features
advanced circuit design to provide ultra low active current.
This is ideal for providing More Battery Life™ (MoBL^®) in
portable applications such as cellular telephones. The device
also has an automatic power down feature that significantly
reduces power consumption by 90% when addresses are not
toggling. The device can also be put into standby mode
reducing power consumption when deselected (CE HIGH or
both BLE and BHE are HIGH). The input and output pins (I/O₀
through I/O₁₅) are placed in a high impedance state when:
deselected (CE HIGH), outputs are disabled (OE HIGH), both
Byte High Enable and Byte Low Enable are disabled (BHE,
BLE HIGH), or during a write operation (CE LOW and WE
LOW).
Writing to the device is accomplished by asserting Chip
Enable (CE) and Write Enable (WE) inputs LOW. If Byte Low
Enable (BLE) is LOW, then data from I/O pins (I/O₀ through
I/O₇), is written into the location specified on the address pins
(A₀ through A₁₆). If Byte High Enable (BHE) is LOW, then data
from I/O pins (I/O₈ through I/O₁₅) is written into the location
specified on the address pins (A₀ through A₁₆).
Reading from the device is accomplished by asserting Chip
Enable (CE) and Output Enable (OE) LOW while forcing the
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,
then data from the memory location specified by the address
pins appears on I/O₀ to I/O₇. If Byte High Enable (BHE) is
LOW, then data from memory appears on I/O₈ to I/O₁₅. See
the Truth Table on page 10 for a complete description of read
and write modes.
The CY62137EV30 is available in 48-ball VFBGA and 44-pin
TSOPII packages.
Logic Block Diagram
AA₁₉₀
A₈
A₇
A₆
A₅
A₄
A₃
A₂
AA₀₁
DATA IN DRIVERS
128K x 16
RAM Array
I/O₀ – I/O₇
I/O₈ – I/O₁₅
COLUMN DECODER
Power -Down
Circuit
CE
BHE
BLE
BHE
WE
CE
OE
BLE
Note
1. For best practice recommendations, refer to the Cypress application note “SRAM System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 38-05443 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 17, 2011
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