CY621282BN Datasheet, PDF (6/12 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM Automatic power-down when deselected

CY621282BN
MoBL^ Automotive
Switching Characteristics Over the Operating Range
Parameter^[7]
Read Cycle
t_RC
t_AA
t_OHA
t_ACE
t_DOE
t_LZOE
t_HZOE
t_LZCE
t_HZCE
t_PU
t_PD
Write Cycle^[10]
t_WC
t_SCE
t_AW
t_HA
t_SA
t_PWE
t_SD
t_HD
t_LZWE
t_HZWE
Description
Read cycle time
Address to data valid
Data hold from address change
CE₁ LOW to data valid, CE₂ HIGH to data valid
OE LOW to data valid
OE LOW to Low Z
OE HIGH to High Z^{[7, 9]}
CE₁ LOW to Low Z, CE₂ HIGH to Low Z^[9]
CE₁ HIGH to High Z, CE₂ LOW to High Z^{[8, 9]}
CE₁ LOW to Power-up, CE₂ HIGH to power-up
CE₁ HIGH to Power-down, CE₂ LOW to power-down
Write cycle time
CE₁ LOW to Write End, CE₂ HIGH to write end
Address set-up to write end
Address hold from write end
Address set-up to write start
WE pulse width
Data set-up to write end
Data Hold from write end
WE HIGH to Low Z^[9]
WE LOW to High Z^{[8, 9]}
CY621282BN-70
Unit
Min
Max
70
–
ns
–
70
ns
5
–
ns
–
70
ns
–
35
ns
0
–
ns
–
25
ns
5
–
ns
–
25
ns
0
–
ns
–
70
ns
70
–
ns
60
–
ns
60
–
ns
0
–
ns
0
–
ns
50
–
ns
30
–
ns
0
–
ns
5
–
ns
–
25
ns
Switching Waveforms
Figure 4. Read Cycle No.1^{[11, 12]}
Address
Data Out
t_RC
t_AA
t_OHA
Previous Data Valid
Data Valid
Notes
7. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5 V, input pulse levels of 0 to 3.0 V, and output loading of the specified
I_OL/I_OH and 100-pF load capacitance.
8. t_HZOE, t_HZCE, and t_HZWE are specified with a load capacitance of 5 pF as in (b) of AC Test Loads. Transition is measured 500 mV from steady-state voltage.
9. At any given temperature and voltage condition, t_HZCE is less than t_LZCE, t_HZOE is less than t_LZOE, and t_HZWE is less than t_LZWE for any given device.
10.
The internal write time of the memory is defined by
write, and the transition of any of these signals can
the overlap of
terminate the
CwErit_1eL. OThWe,
iCnpEu²t
HIGH, and WE LOW.
data set-up and hold
tCimEi¹ngansdhoWuEld
mbeusrtebfeereLnOcWedatnodthCeEle_{2 aHdIiGngH}
to initiate a
edge of the
signal that terminates the write.
11. Device is continuously selected. OE, CE₁ = V_IL, CE₂ = V_IH.
12. WE is HIGH for read cycle.
Document #: 001-65526 Rev. **
Page 6 of 12
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