CY621282BN Datasheet, PDF (1/12 Pages) Cypress Semiconductor – 1-Mbit (128K x 8) Static RAM Automatic power-down when deselected

CY621282BN
MoBL^ Automotive
1-Mbit (128K x 8) Static RAM
Features
■ Temperature Ranges
❐ Automotive-E: –40 °C to 125 °C
■ 4.5 V – 5.5 V operation
■ Complementary metal oxide semiconductor (CMOS) for
optimum speed/power
■ Low active power
137.5 mW (max.) (25 mA)
■ Low standby power
137.5 W (max.) (25 A)
■ Automatic power-down when deselected
■ TTL-compatible inputs and outputs
■ Easy memory expansion with CE₁, CE₂, and OE options
■ Available in Pb-free 32-pin (450 mil-wide) small outline
integrated circuit (SOIC) package
Functional Description
The CY621282BN^[1] is a high-performance CMOS static RAM
organized as 128K words by 8 bits. Easy memory expansion is
provided by an active LOW Chip Enable (CE₁), an active HIGH
Chip Enable (CE₂), and active LOW Output Enable (OE). This
device has an automatic power-down feature that reduces power
consumption by more than 75% when deselected.
Writing to the device is accomplished by taking Chip Enable One
(CE₁) and Write Enable (WE) inputs LOW and Chip Enable Two
(CE₂) input HIGH. Data on the eight I/O pins (I/O₀ through I/O₇)
is then written into the location specified on the address pins (A₀
through A₁₆).
Reading from the device is accomplished by taking Chip Enable
One (CE₁) and Output Enable (OE) LOW while forcing Write
Enable (WE) and Chip Enable Two (CE₂) HIGH. Under these
conditions, the contents of the memory location specified by the
address pins will appear on the I/O pins.
The eight input/output pins (I/O₀ through I/O₇) are placed in a
high-impedance state when the device is deselected (CE₁ HIGH
or CE₂ LOW), the outputs are disabled (OE HIGH), or during a
write operation (CE₁ LOW, CE₂ HIGH, and WE LOW).
Logic Block Diagram
A0
A1
A2
A3
A4
A5
A6
A7
A8
CCEE12
WE
OE
INPUT BUFFER
128K x 8
ARRAY
COLUMN
DECODER
POWER
DOWN
I/O ₀
I/O ₁
I/O ₂
I/O ₃
I/O ₄
I/O ₅
I/O ₆
I/O ₇
Note
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.
Cypress Semiconductor Corporation • 198 Champion Court
Document #: 001-65526 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 6, 2011
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