CY2XP31ZXC Datasheet, PDF (6/8 Pages) Cypress Semiconductor – 312.5 MHz LVPECL Clock Generator

CY2XP41
Application Information
Power Supply Filtering Techniques
As in any high speed analog circuitry, noise at the power supply
pins degrades performance. To achieve optimum jitter perfor-
mance, good power supply isolation practices are advised.
Figure 6. shows a typical filtering scheme. Since all of the current
flows through pin 1, the resistance and inductance between this
pin and the supply is minimized. A 0.01 or 0.1 µF ceramic chip
capacitor is also located close to this pin to provide a short and
low impedance AC path to ground. A ~5 to 10 µF tantalum
capacitor is also located in the vicinity of this device.
Figure 6. Power Supply Filtering
V _DD
(Pin 8)
Crystal Input Interface
The CY2XP41 is characterized with 10 pF parallel resonant
crystals. The capacitor values shown in Figure 7. are determined
using a 25 MHz 10 pF parallel resonant crystal and are chosen
to minimize the ppm error. Cypress recommends the
following C1 and C2 values: C1 = C2 = 6.8pF.
Figure 7. Crystal Input Interface
External
Crystal
XIN
C1
XOUT
C2
VDD
(Pin 1)
3.3V
0₀._.1₀μ₁F_{µF 10µF}
Termination for 3.3V LVPECL Output
CLK and CLK# are pull up drivers that generate ECL/LVPECL
compatible outputs. Therefore, terminating resistors (DC current
path to ground) or current sources are used for functionality.
Matched impedance techniques are used to maximize operating
frequency and minimize signal distortion. Figure 2 on page 5
shows a termination scheme that is recommended as a
guideline. Other suitable clock layouts exist and it is recom-
mended that the board designers simulate to guarantee compat-
ibility across all printed circuit and process variations. Cypress
recommends the following RU and RD values: RU=110Ω and
RD=62Ω. This is a 40Ω load, which is used to achieve the
specified common mode and peak-to-peak voltage swing. For
optimal signal integrity, 40Ω traces are recommended.
Document #: 001-48923 Rev. *A
Page 6 of 8
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