CY2XP31ZXC Datasheet, PDF (3/8 Pages) Cypress Semiconductor – 312.5 MHz LVPECL Clock Generator

CY2XP41
Frequency Table
Input
Input Xtal Frequency (MHz)
25
25
Output Frequency (MHz)
FS
0
62.5
1
75.0
Absolute Maximum Conditions
Parameter
V_DD
V_IN[1.]
T_S
T_J
ESD_HBM
UL–94
Θ_JA[2]
Description
Condition
Supply Voltage
Input Voltage, DC
Relative to VSS
Temperature, Storage
Non Functional
Temperature, Junction
ESD Protection (Human Body Model) JEDEC STD 22-A114-B
Flammability Rating
At 1/8 in.
Thermal Resistance, Junction to
Ambient
0 m/s airflow
1 m/s airflow
2.5 m/s airflow
Operating Conditions
Parameter
Description
V_DD
3.3V Supply Voltage
T_A
Ambient Temperature, Commercial
T_PU
Power up time for all V_DD to reach minimum specified voltage (ensure power
ramps are monotonic)
Min
–0.5
–0.5
–65
2000
Max
4.4
V_DD + 0.5
150
135
V–0
100
91
87
Unit
V
V
°C
°C
V
°C/W
Min
3.135
0
0.05
Max
Unit
3.465
V
70
°C
500
ms
Electrical Characteristics for Input
Parameter
Description
V_IL
Input Low Voltage
V_IH
Input High Voltage
I_IL
Input Low Current
I_IH
Input High Current
C_IN
Input Capacitance
Test Conditions
FS = V_SS
FS = V_DD
DC Electrical Characteristics for Power Supplies
Parameter
Description
I_DD[3]
Power Supply Current with output terminated
Min
–
0.7*V_DD
–50
–
Typ Max
– 0.3*V_DD
–
–
–
–
–
115
15
Unit
V
V
µA
µA
pF
Min Typ Max Unit
–
–
180
mA
Note
1. The voltage on any input or IO pin cannot exceed the power pin during power up. Power supply sequencing is NOT required.
2. Simulated using Apache Sentinel TI software. The board is derived from the JEDEC multilayer standard. It measures 76 x 114 x 1.6 mm and has 4-layers of
copper (2/1/1/2 oz.). The internal layers are 100% copper planes, while the top and bottom layers have 50% metallization. No vias are included in the model.
3. I_DD includes ~16 mA of current that is dissipated externally in the output termination resistors.
Document #: 001-48923 Rev. *A
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