CY2XP306 Datasheet, PDF (6/9 Pages) Cypress Semiconductor – High-frequency Programmable PECL Clock Generation Module

PRELIMINARY
CY2XP306
AC Specifications (V_DD = 3.3 V ± 5%, Commercial and Industrial Temperature)
Parameter
Description
Conditions
Min. Typ. Max. Unit
f_IN
f_XTALIN
C_IN,CMOS
Input frequency
Limited by Max PLL Frequency
Crystal Input frequency
Input capacitance at PLL_MULT
pin^[4]
1
– 133 MHz
10 – 31.25 MHz
–
– 10 pF
f_O
Vo_(P-P)
Output Frequency
Differential output voltage
(peak-to-peak)
125 – 500 MHz
0.5 –
–V
V_CMRO
tsk_(O)
Output Common Voltage Range Typical
Output-to-output skew
311 MHz 50% duty cycle Standard load Differential
Operation
V_DD – 1.425
V
– 30 TBD ps
tsk_(PP)
Part-to-part output skew
311 MHz 50% duty cycle Standard load Differential –
Operation
– 150 ps
T_R,T_F
DC
Output Rise / Fall time
311 MHz 50% duty cycle Differential (20% to 80%) –
– 0.3 ns
Long-term average output duty
cycle
45 – 55 %
J_C2C
Cycle-to-cycle Jitter (Peak)
peak; 311 MHz; Jitter Defined by JESD65B
– 60 TBD ps
tr, tf,
VO
20-80%
Figure 5. LVPECL Output
Notes:
4. Capacitance measured at freq. = 1 MHz, DC Bias = 0.9V, and VAC < 100 mV.
Document #: 38-07725 Rev. *A
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