CY2XP306 Datasheet, PDF (1/9 Pages) Cypress Semiconductor – High-frequency Programmable PECL Clock Generation Module

PRELIMINARY
CY2XP306
High-frequency Programmable PECL Clock Generation Module
Features
• 60 ps typical Cycle-to-Cycle Jitter
• 30 ps typical Output-Output Skew
• Phase-locked loop (PLL) multiplier select
• LVTTL or XO Input; Six LVPECL Outputs
• Selectable Output Divider (/2)
Block Diagram
FSELA
PLL_MULT
XIN/REF
XOUT
SER CLK
SER DATA
XTAL
PLL
OSCILLATOR
xM
MR
FSELB
Pin Configuration (Top View)
C Y 2X P 306 36 V FB G A P IN C O N F IG U R A T IO N
QA1
6
5
VDDA
GND
4
XOUT
3
XIN
2
VDDB
1
A
QA1#
GND
SER_
DATA
SER_
CLK
GND
VDDB
B
QA2
QB2
QB2#
GND
C
QA2#
PLL_
M ULT
D
• 1–133 MHz Input Frequency Range
• 62.5–500 MHz Output Frequency Range
• 36-pin VFBGA, 6 × 8 × 1 mm
• 3.3V operation
• Serially Configurable Multiply Ratios
0
1
/1
/2
0
1
QA1
QA1#
QA2
QA2#
QA3
QA3#
QB1
QB1#
QB2
QB2#
QB3
QB3#
T O P V IE W
QA3
QA3#
QB1
QB3
GND
VDDB
QB3#
VDDB
GND
MR
FSELA
FSELB
E
F
G
QB1#
VDDA
VDDA
NC
VDDA
VDDA
H
Cypress Semiconductor Corporation • 3901 North First Street • San Jose, CA 95134 • 408-943-2600
Document #: 38-07725 Rev. *A
Revised April 8, 2005