CY27EE16ZE Datasheet, PDF (6/17 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

CY27EE16ZE
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Table 5. Programmable External Reference Input Oscillator Drive Settings
Reference Frequency
Drive Setting
1 – 25 MHz
00
25 – 50 MHz
01
50 – 90 MHz
10
90 – 167 MHz
11
Using an External Clock as the Reference Input
The CY27EE16ZE can also accept an external clock as
reference, with speeds up to 167 MHz (or 150 MHz at Indus-
trial Temp.). With an external clock, the XDRV (register 12H)
bits must be set according to Table 5.
Input Load Capacitors
Input load capacitors allow the user to set the load capacitance
of the CY27EE16ZE to match the input load capacitance from
a crystal. The value of the input load capacitors is determined
by 8 bits in a programmable register [13H]. The proper
CapLoad register setting is determined by the formula:
CapLoad = (C_L– C_BRD – C_CHIP)/0.09375 pF
where:
• C_L = specified load capacitance of your crystal.
• C_BRD = the total board capacitance, due to external capac-
itors and board trace capacitance. In CyClocksRT, this value
defaults to 2 pF.
• C_CHIP = 6 pF.
• 0.09375 pF = the step resolution available due to the 8-bit
register.
In CyclocksRT, only the crystal capacitance (C_L) is specified.
C_CHIP is set to 6 pF, and C_BRD defaults to 2 pF. If your board
capacitance is higher or lower than 2 pF, the formula above
can be used to calculate a new CapLoad value and
programmed into register 13H.
In CyClocksRT, enter the crystal capacitance (C_L). The value
of CapLoad will be determined automatically and programmed
into the CY27EE16ZE. Through the SDAT and SCLK pins, the
value can be adjusted up or down if your board capacitance is
greater or less than 2 pF. For an external clock source,
CapLoad defaults to 1. See Table 6 for CapLoad bit locations
and values.
The input load capacitors are placed on the CY27EE16ZE die
to reduce external component cost. These capacitors are true
parallel-plate capacitors, designed to reduce the frequency
shift that occurs when non-linear load capacitance is affected
by load, bias, supply and temperature changes
DCXO/VCXO
The default clock configuration of the CY27EE16ZE has 256
stored values that are used to adjust the frequency of the
crystal oscillator, by changing the load capacitance. In order to
use these stored values, the clock configuration must be
reprogrammed to enable the DCXO or VCXO feature.
To Configure for DCXO Operation
1. FTAAddrScr[1:0], Register 12H[7:6] = 00 (default configu-
ration = 00)
2. XCapSrc, Register 12H[5] = 0
3. XDRV[1:0], Register 12H[4:3] = (see Table 3)
4. ADCEnable, Register 14H[7] = 0
5. ADCBypCnt, Register 14H[6] = 0
6. ADCCnt[2:0], Register 14H[5:3] = 000
7. ADCFilt[1:0], Register 14H[2:1] = 00
Once the clock configuration block is programmed for DCXO
operation, the SPI may be used to dynamically change the
capacitor load value on the crystal. A change in crystal load
capacitance corresponds with a change in the reference
frequency. Thus, the crystal oscillator frequency can be
adjusted from –150 ppm of the nominal frequency value to
+150 ppm of the nominal frequency value. “Nominal frequency
– 150 ppm” is achieved by writing 00000000 into the CapLoad
register, and “nominal frequency + 150 ppm” is achieved by
writing 11111111 into the CapLoad register
Configure for VCXO Operation
To configure the VCXO for analog control clock configuration
registers must be written to as follows:
1. FTAAddrSrc[1:0], Register 12H[7:6] = 01
2. XCapSrc, Register 12H[5] = 0
3. XDRV[1:0], Register 12H[4:3] = (see Table 3)
4. ADCEnable, Register 14H[7] = 1
5. ADCBypCnt, Register 14H[6] = 0
6. ADCCnt[2:0], = 001
7. ADCFilt[1:0], Register 14H[2:1]= 10
8. WPSrc, Register 11H[3] = 1
Table 6. Input Load Capacitor Register Bit Setting
Address
D7
D6
D5
D4
D3
D2
D1
D0
13H
CapLoad(7) CapLoad(6) CapLoad(5) CapLoad(4) CapLoad(3) CapLoad(2) CapLoad(1) CapLoad(0)
Document #: 38-07440 Rev. *B
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