CY27EE16ZE Datasheet, PDF (5/17 Pages) Cypress Semiconductor – 1 PLL In-System Programmable Clock Generator with Individual 16K EEPROM

DIV1N [OCH]
DIV1SRC [OCH]
1
Q_total
REF
(Q+2)
PFD
VCO
0
[42H]
P_total
(2(PB+4)+PO)
[40H], [41H], [42H]
1
0
CY27EE16ZE
/DIV1N
/2
/3
Divider Bank 1
Divider Bank 2
/4
/2
/DIV2N
CLKSRC
Crosspoint
Switch Matrix
[44H]
[44H]
[44H,45H]
[45H]
[45H,46h]
[46H]
CLOCK1
CLOCK2
CLOCK3
CLOCK4
CLOCK5
CLOCK6
DIV2SRC [47H]
DIV2N [47H]
CLKOE [09H]
Figure 2. Basic Block Diagram of CY27EE16ZE PLL
Reference Frequency (REF)
The reference frequency can be a crystal or a driven
frequency. For crystals, the frequency range must be between
8 MHz and 30 MHz. For a driven frequency, the frequency
range must be between 1 MHz and 167 MHz (Commercial
Temp.) or 150 MHz (Industrial Temp.).
Using a Crystal as the Reference Input
The input crystal oscillator of the CY27EE16ZE is an important
feature because of the flexibility it allows the user in selecting
a crystal as a reference frequency source. The input oscillator
has programmable gain, allowing for maximum compatibility
with a reference crystal, regardless of manufacturer, process,
performance and quality.
Programmable Crystal Input Oscillator Gain Settings
The Input crystal oscillator gain (XDRV) is controlled by two
bits in register 12H, and are set according to Table 3. The
parameters controlling the gain are the crystal frequency, the
internal crystal parasitic resistance (ESR, available from the
manufacturer), and the CapLoad setting during crystal
start-up.
Bits 3 and 4 of register 12H control the input crystal oscillator
gain setting. Bit 4 is the MSB of the setting, and bit 3 is the
LSB. The setting is programmed according to Table 3.
All other bits in the register are reserved and should be
programmed LOW. See Table 4 for bit locations and values.
Table 3. Programmable Crystal Input Oscillator Gain Settings
Calculated CapLoad Value
Crystal ESR
Crystal Input
Frequency
8 – 15 MHz
15 – 20 MHz
20 – 25 MHz
25 – 30 MHz
00H – 20H
30Ω
60Ω
00
01
01
10
01
10
10
10
20H – 30H
30Ω
60Ω
01
10
01
10
10
10
10
11
30H – 40H
30Ω
60Ω
01
10
10
10
10
11
11
N/A
Table 4. Register Map for Input Crystal Oscillator Gain Setting
Address
12H
D7
FTAAddrSrc(1)
default=0
D6
FTAAddrSrc(0)
default=0
D5
D4
D3
D2 D1 D0
XCapSrc XDRV(1) XDRV(0) 0
0
0
default=1
Document #: 38-07440 Rev. *B
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